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[Arch] Patch embedded I/O example architecture

This commit is contained in:
tangxifan 2020-11-02 15:16:19 -07:00
parent 7e9e0ec9d4
commit c512644a09
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
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@ -188,14 +188,14 @@
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="PAD" lib_name="A" size="1" is_global="true" is_io="true" />
<port type="inout" prefix="PAD" lib_name="A" size="1" is_global="true" is_io="true" />
<port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model>
<circuit_model type="iopad" name="GPOUT" prefix="GPOUT" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="output" prefix="PAD" lib_name="Y" size="1" is_global="true" is_io="true" />
<port type="inout" prefix="PAD" lib_name="Y" size="1" is_global="true" is_io="true" />
<port type="input" prefix="outpad" lib_name="A" size="1"/>
</circuit_model>
</circuit_library>