From c512644a090b4f681c1b01a99d8992c51697ef7b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 2 Nov 2020 15:16:19 -0700
Subject: [PATCH] [Arch] Patch embedded I/O example architecture

---
 ..._scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
index 33139e6de..ccb9629a8 100644
--- a/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -188,14 +188,14 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <port type="input" prefix="PAD" lib_name="A" size="1" is_global="true" is_io="true" />
+      <port type="inout" prefix="PAD" lib_name="A" size="1" is_global="true" is_io="true" />
       <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
     <circuit_model type="iopad" name="GPOUT" prefix="GPOUT" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <port type="output" prefix="PAD" lib_name="Y" size="1" is_global="true" is_io="true" />
+      <port type="inout" prefix="PAD" lib_name="Y" size="1" is_global="true" is_io="true" />
       <port type="input" prefix="outpad" lib_name="A" size="1"/>
     </circuit_model>
   </circuit_library>