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bug fix in the frac memory & DSP architecture

This commit is contained in:
tangxifan 2020-08-18 15:05:51 -06:00
parent 21c7eaa9cf
commit 098859fe06
1 changed files with 23 additions and 23 deletions
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46
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
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@ -315,7 +315,7 @@
<port name="clk" physical_mode_port="clk"/>
</pb_type>
<!-- Bind the 1024x32 single port RAM to the physical implementation -->
<pb_type name="memory[mem_1024x32_sp].mem_1024x32_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0000">
<pb_type name="memory[mem_1024x32_sp].mem_1024x32_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0001">
<port name="addr" physical_mode_port="addr1[0:9]"/>
<port name="data" physical_mode_port="data1"/>
<port name="we" physical_mode_port="we1"/>
@ -323,7 +323,7 @@
<port name="clk" physical_mode_port="clk"/>
</pb_type>
<!-- Bind the 2048x16 single port RAM to the physical implementation -->
<pb_type name="memory[mem_2048x16_sp].mem_2048x16_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0001">
<pb_type name="memory[mem_2048x16_sp].mem_2048x16_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0010">
<port name="addr" physical_mode_port="addr1[0:10]"/>
<port name="data" physical_mode_port="data1[0:15]"/>
<port name="we" physical_mode_port="we1"/>
@ -331,7 +331,7 @@
<port name="clk" physical_mode_port="clk"/>
</pb_type>
<!-- Bind the 4096x8 single port RAM to the physical implementation -->
<pb_type name="memory[mem_4096x8_sp].mem_4096x8_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0010">
<pb_type name="memory[mem_4096x8_sp].mem_4096x8_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0011">
<port name="addr" physical_mode_port="addr1[0:11]"/>
<port name="data" physical_mode_port="data1[0:7]"/>
<port name="we" physical_mode_port="we1"/>
@ -339,7 +339,7 @@
<port name="clk" physical_mode_port="clk"/>
</pb_type>
<!-- Bind the 8192x4 single port RAM to the physical implementation -->
<pb_type name="memory[mem_8192x4_sp].mem_8192x4_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0011">
<pb_type name="memory[mem_8192x4_sp].mem_8192x4_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0100">
<port name="addr" physical_mode_port="addr1[0:12]"/>
<port name="data" physical_mode_port="data1[0:3]"/>
<port name="we" physical_mode_port="we1"/>
@ -347,7 +347,7 @@
<port name="clk" physical_mode_port="clk"/>
</pb_type>
<!-- Bind the 16384x2 single port RAM to the physical implementation -->
<pb_type name="memory[mem_16384x2_sp].mem_16384x2_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0100">
<pb_type name="memory[mem_16384x2_sp].mem_16384x2_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0101">
<port name="addr" physical_mode_port="addr1[0:13]"/>
<port name="data" physical_mode_port="data1[0:1]"/>
<port name="we" physical_mode_port="we1"/>
@ -355,7 +355,7 @@
<port name="clk" physical_mode_port="clk"/>
</pb_type>
<!-- Bind the 32768x1 single port RAM to the physical implementation -->
<pb_type name="memory[mem_32768x1_sp].mem_32768x1_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0101">
<pb_type name="memory[mem_32768x1_sp].mem_32768x1_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0110">
<port name="addr" physical_mode_port="addr1[0:14]"/>
<port name="data" physical_mode_port="data1[0:0]"/>
<port name="we" physical_mode_port="we1"/>
@ -363,18 +363,6 @@
<port name="clk" physical_mode_port="clk"/>
</pb_type>
<!-- Bind the 1024x32 dual port RAM to the physical implementation -->
<pb_type name="memory[mem_1024x32_dp].mem_1024x32_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0110">
<port name="addr1" physical_mode_port="addr1[0:9]"/>
<port name="addr2" physical_mode_port="addr2[0:9]"/>
<port name="data1" physical_mode_port="data1[0:31]"/>
<port name="data2" physical_mode_port="data2[0:31]"/>
<port name="we1" physical_mode_port="we1"/>
<port name="we2" physical_mode_port="we2"/>
<port name="out1" physical_mode_port="out1[0:31]"/>
<port name="out2" physical_mode_port="out2[0:31]"/>
<port name="clk" physical_mode_port="clk"/>
</pb_type>
<!-- Bind the 1024x32 dual port RAM to the physical implementation -->
<pb_type name="memory[mem_1024x32_dp].mem_1024x32_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0111">
<port name="addr1" physical_mode_port="addr1[0:9]"/>
<port name="addr2" physical_mode_port="addr2[0:9]"/>
@ -386,8 +374,20 @@
<port name="out2" physical_mode_port="out2[0:31]"/>
<port name="clk" physical_mode_port="clk"/>
</pb_type>
<!-- Bind the 1024x32 dual port RAM to the physical implementation -->
<pb_type name="memory[mem_1024x32_dp].mem_1024x32_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1000">
<port name="addr1" physical_mode_port="addr1[0:9]"/>
<port name="addr2" physical_mode_port="addr2[0:9]"/>
<port name="data1" physical_mode_port="data1[0:31]"/>
<port name="data2" physical_mode_port="data2[0:31]"/>
<port name="we1" physical_mode_port="we1"/>
<port name="we2" physical_mode_port="we2"/>
<port name="out1" physical_mode_port="out1[0:31]"/>
<port name="out2" physical_mode_port="out2[0:31]"/>
<port name="clk" physical_mode_port="clk"/>
</pb_type>
<!-- Bind the 2048x16 dual port RAM to the physical implementation -->
<pb_type name="memory[mem_2048x16_dp].mem_2048x16_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1000">
<pb_type name="memory[mem_2048x16_dp].mem_2048x16_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1001">
<port name="addr1" physical_mode_port="addr1[0:10]"/>
<port name="addr2" physical_mode_port="addr2[0:10]"/>
<port name="data1" physical_mode_port="data1[0:15]"/>
@ -399,7 +399,7 @@
<port name="clk" physical_mode_port="clk"/>
</pb_type>
<!-- Bind the 4096x8 dual port RAM to the physical implementation -->
<pb_type name="memory[mem_4096x8_dp].mem_4096x8_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1001">
<pb_type name="memory[mem_4096x8_dp].mem_4096x8_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1010">
<port name="addr1" physical_mode_port="addr1[0:11]"/>
<port name="addr2" physical_mode_port="addr2[0:11]"/>
<port name="data1" physical_mode_port="data1[0:7]"/>
@ -411,7 +411,7 @@
<port name="clk" physical_mode_port="clk"/>
</pb_type>
<!-- Bind the 8192x4 dual port RAM to the physical implementation -->
<pb_type name="memory[mem_8192x4_dp].mem_8192x4_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1010">
<pb_type name="memory[mem_8192x4_dp].mem_8192x4_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1011">
<port name="addr1" physical_mode_port="addr1[0:12]"/>
<port name="addr2" physical_mode_port="addr2[0:12]"/>
<port name="data1" physical_mode_port="data1[0:3]"/>
@ -423,7 +423,7 @@
<port name="clk" physical_mode_port="clk"/>
</pb_type>
<!-- Bind the 16384x2 dual port RAM to the physical implementation -->
<pb_type name="memory[mem_16384x2_dp].mem_16384x2_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1011">
<pb_type name="memory[mem_16384x2_dp].mem_16384x2_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1100">
<port name="addr1" physical_mode_port="addr1[0:13]"/>
<port name="addr2" physical_mode_port="addr2[0:13]"/>
<port name="data1" physical_mode_port="data1[0:1]"/>
@ -435,7 +435,7 @@
<port name="clk" physical_mode_port="clk"/>
</pb_type>
<!-- Bind the 32768x1 dual port RAM to the physical implementation -->
<pb_type name="memory[mem_32768x1_dp].mem_32768x1_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1100">
<pb_type name="memory[mem_32768x1_dp].mem_32768x1_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1101">
<port name="addr1" physical_mode_port="addr1[0:14]"/>
<port name="addr2" physical_mode_port="addr2[0:14]"/>
<port name="data1" physical_mode_port="data1[0:0]"/>