[Architecture] Remove out-of-date Verilog testbench
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//-----------------------------------------------------
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// Design Name : testbench for logic blocks
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// File Name : lb_tb.v
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// Function : Configurable logic block
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// Coder : Xifan TANG
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//-----------------------------------------------------
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//----- Time scale: simulation time step and accuracy -----
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`timescale 1ns / 1ps
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module lb_tb;
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// Parameters
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parameter SIZE_IN = 40; //---- MUX input size
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parameter SIZE_OUT = 10; //---- MUX input size
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parameter SIZE_RESERV_BLWL = 49 + 1; //---- MUX input size
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parameter SIZE_BLWL = 1019 - 310 + 1; //---- MUX input size
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parameter prog_clk_period = 1; // [ns] half clock period
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parameter op_clk_period = 1; // [ns] half clock period
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parameter config_period = 2 * prog_clk_period; // [ns] One full clock period
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parameter operating_period = SIZE_IN * 2 * op_clk_period; // [ns] One full clock period
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// Ports
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wire [0:SIZE_IN-1] lb_in;
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wire [0:SIZE_IN-1] lb_out;
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wire lb_clk;
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wire [0:SIZE_RESERV_BLWL-1] reserv_bl;
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wire [0:SIZE_RESERV_BLWL-1] reserv_wl;
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wire [0:SIZE_BLWL-1] bl;
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wire [0:SIZE_BLWL-1] wl;
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wire prog_EN;
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wire prog_ENb;
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wire zin;
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wire nequalize;
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wire read;
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wire clk;
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wire Reset;
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wire Set;
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// Clocks
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wire prog_clock;
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wire op_clock;
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// Registered port
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reg [0:SIZE_IN-1] lb_in_reg;
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reg [0:SIZE_RESERV_BLWL-1] reserv_bl_reg;
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reg [0:SIZE_RESERV_BLWL-1] reserv_wl_reg;
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reg [0:SIZE_BLWL-1] bl_reg;
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reg [0:SIZE_BLWL-1] wl_reg;
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reg prog_clock_reg;
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reg op_clock_reg;
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// Config done signal;
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reg config_done;
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// Temp register for rotating shift
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reg temp;
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// Unit under test
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grid_1__1_ U0 (
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zin,
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nequalize,
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read,
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clk,
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Reset,
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Set,
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prog_ENb,
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prog_EN,
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// Top inputs
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lb_in[0], lb_in[4], lb_in[8], lb_in[12], lb_in[16],
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lb_in[20], lb_in[24], lb_in[28], lb_in[32], lb_in[36],
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// Top outputs
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lb_out[0], lb_out[4], lb_out[8],
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// Right inputs
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lb_in[1], lb_in[5], lb_in[9], lb_in[13], lb_in[17],
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lb_in[21], lb_in[25], lb_in[29], lb_in[33], lb_in[37],
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// Right outputs
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lb_out[1], lb_out[5], lb_out[9],
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// Bottom inputs
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lb_in[2], lb_in[6], lb_in[10], lb_in[14], lb_in[18],
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lb_in[22], lb_in[26], lb_in[30], lb_in[34], lb_in[38],
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// Bottom outputs
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lb_out[2], lb_out[6],
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// Bottom inputs
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lb_clk,
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// left inputs
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lb_in[3], lb_in[7], lb_in[11], lb_in[15], lb_in[19],
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lb_in[23], lb_in[27], lb_in[31], lb_in[35], lb_in[39],
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// left outputs
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lb_out[3], lb_out[7],
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reserv_bl, reserv_wl,
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bl, wl
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);
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// Task: assign BL and WL values
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task prog_lb_blwl;
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begin
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@(posedge prog_clock);
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// Rotate left shift
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temp = reserv_bl_reg[SIZE_RESERV_BLWL-1];
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//bl_reg = bl_reg >> 1;
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reserv_bl_reg[1:SIZE_RESERV_BLWL-1] = reserv_bl_reg[0:SIZE_RESERV_BLWL-2];
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reserv_bl_reg[0] = temp;
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end
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endtask
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// Task: assign inputs
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task op_lb_in;
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begin
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@(posedge op_clock);
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temp = lb_in_reg[SIZE_IN-1];
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lb_in_reg[1:SIZE_IN-1] = lb_in_reg[0:SIZE_IN-2];
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lb_in_reg[0] = temp;
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end
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endtask
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// Configuration done signal
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initial
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begin
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config_done = 1'b0;
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end
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// Enabled during config_period, Disabled during op_period
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always
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begin
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#config_period config_done = ~config_done;
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#operating_period config_done = ~config_done;
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end
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// Programming clocks
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initial
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begin
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prog_clock_reg = 1'b0;
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end
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always
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begin
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#prog_clk_period prog_clock_reg = ~prog_clock_reg;
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end
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// Operating clocks
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initial
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begin
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op_clock_reg = 1'b0;
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end
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always
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begin
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#op_clk_period op_clock_reg = ~op_clock_reg;
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end
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// Programming and Operating clocks
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assign prog_clock = prog_clock_reg & (~config_done);
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assign op_clock = op_clock_reg & config_done;
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// Programming Enable signals
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assign prog_EN = prog_clock & (~config_done);
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assign prog_ENb = ~prog_EN;
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// Programming phase: BL/WL
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initial
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begin
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// Initialize BL/WL registers
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reserv_bl_reg = {SIZE_RESERV_BLWL {1'b0}};
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reserv_bl_reg[0] = 1'b1;
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reserv_wl_reg = {SIZE_RESERV_BLWL {1'b0}};
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// Reserved BL/WL
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bl_reg = {SIZE_BLWL {1'b0}};
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wl_reg = {SIZE_BLWL {1'b1}};
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//wl_reg[SIZE_BLWL-1] = 1'b1;
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end
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always wait (~config_done) // Only invoked when config_done is 0
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begin
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// Propagate input 1 to the output
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// BL[0] = 1, WL[4] = 1
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prog_lb_blwl;
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end
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// Operating Phase
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initial
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begin
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lb_in_reg = {SIZE_IN {1'b0}};
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lb_in_reg[0] = 1'b1; // Last bit is 1 initially
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end
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always wait (config_done) // Only invoked when config_done is 1
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begin
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/* Update inputs */
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op_lb_in;
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end
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// Wire ports
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assign lb_in = lb_in_reg;
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assign reserv_bl = reserv_bl_reg;
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assign reserv_wl = reserv_wl_reg;
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assign bl = bl_reg;
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assign wl = wl_reg;
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// Constant ports
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assign zin = 1'b0;
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assign nequalize = 1'b1;
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assign read = 1'b0;
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assign clk = op_clock;
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assign Reset = ~config_done;
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assign Set = 1'b0;
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endmodule
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