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Code Issues Projects Releases Wiki Activity

comment out desings that utilize local async reset/preset

This commit is contained in:
Tarachand Pagarani 2021-03-09 19:24:01 -08:00
parent 7f4c20ff33
commit 608bd1f658
1 changed files with 2 additions and 1 deletions
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3
openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
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@ -46,7 +46,8 @@ bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/diffeq_f
#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/i2c_master_top/rtl/*.v
#iir requires async reset/preset
#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/iir/rtl/*.v
bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr/rtl/*.v
#jpeg_qnr requires async reset/preset
#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr/rtl/*.v
bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/*.v
# sdc_controller requires 4 clocks
#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sdc_controller/rtl/*.v