From 608bd1f658cc6701e7e05bae9a49e611bdb77710 Mon Sep 17 00:00:00 2001 From: Tarachand Pagarani Date: Tue, 9 Mar 2021 19:24:01 -0800 Subject: [PATCH] comment out desings that utilize local async reset/preset --- .../tasks/quicklogic_tests/flow_test/config/task.conf | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf index 43e7649b8..c21d40b7e 100644 --- a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf @@ -46,7 +46,8 @@ bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/diffeq_f #bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/i2c_master_top/rtl/*.v #iir requires async reset/preset #bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/iir/rtl/*.v -bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr/rtl/*.v +#jpeg_qnr requires async reset/preset +#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr/rtl/*.v bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/*.v # sdc_controller requires 4 clocks #bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sdc_controller/rtl/*.v