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Merge branch 'master' into default_net_type

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tangxifan 2021-03-01 08:38:58 -07:00 committed by GitHub
parent 521e1850c8 8e89da5966
commit e34380a654
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12 changed files with 111 additions and 30 deletions
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10
libopenfpga/libarchopenfpga/src/circuit_library.cpp
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@ -1214,6 +1214,16 @@ CircuitModelId CircuitLibrary::add_model(const enum e_circuit_model_type& type)
/* Build the fast look-up for circuit models */
build_model_lookup();
/* Add a placeholder in the fast look-up for model port
* This is to avoid memory holes when a circuit model
* does not have any ports.
* As a result, the fast look-up may not even create an entry
* for this model id, which cause fast look-up abort when there is
* a query on the model
*/
model_port_lookup_.resize(model_ids_.size());
model_port_lookup_[model_id].resize(NUM_CIRCUIT_MODEL_PORT_TYPES);
return model_id;
}

18
openfpga/src/repack/repack.cpp
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@ -259,13 +259,25 @@ std::vector<int> find_pb_route_remapped_source_pb_pin(const t_pb* pb,
/* Only care the pin has the same parent port as source_pb_pin
* Due to that the source_pb_pin may be swapped during routing
* the pb_route is out-of-date
*
* For those parent port is defined as non-equivalent,
* the source pin and the pin recorded in the routing trace must match!
*
* TODO: should update pb_route by post routing results
* On the other side, the swapping can only happen between equivalent pins
* in a port. So the port must match here!
*/
if (source_pb_pin->port == pb->pb_route.at(pin).pb_graph_pin->port) {
pb_route_indices.push_back(pin);
}
if (PortEquivalence::FULL == source_pb_pin->port->equivalent) {
if (source_pb_pin->port == pb->pb_route.at(pin).pb_graph_pin->port) {
pb_route_indices.push_back(pin);
}
} else {
/* NOTE: INSTANCE is NOT supported! We support only NONE equivalent */
VTR_ASSERT (PortEquivalence::NONE == source_pb_pin->port->equivalent);
if (source_pb_pin == pb->pb_route.at(pin).pb_graph_pin) {
pb_route_indices.push_back(pin);
}
}
}
return pb_route_indices;

2
openfpga_flow/misc/qlf_yosys.ys
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@ -2,5 +2,5 @@
# Read verilog files
${READ_VERILOG_FILE}
synth_quicklogic -blif ${OUTPUT_BLIF} -openfpga -top ${TOP_MODULE}
synth_quicklogic -blif ${OUTPUT_BLIF} -family qlf_k4n8 -no_adder -top ${TOP_MODULE}

12
openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
View File

@ -197,6 +197,18 @@
<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="DFFRQ" default_val="1"/>
</circuit_model>
<!-- dummy circuit model pointer.
The idea is just to include the netlist for HDL simulation
TODO: This feature SHOULD be supported as an option in write_verilog_testbench command
The key idea here is that the openfpga arch XML should focus on physical design aspects
Anything related to simulation should be classified in the simulation settings or shell script
-->
<!-- A dummy model to include the adder_lut verilog code in testbench netlists
so that HDL simulation can be run when adder lut is used in users' implementations
-->
<!--circuit_model type="inv_buf" name="dummy1" prefix="dummy1" verilog_netlist="${OPENFPGA_PATH}/yosys/techlibs/quicklogic/openfpga_cells_sim.v">
<design_technology type="cmos" topology="inverter" size="1"/>
</circuit_model-->
</circuit_library>
<configuration_protocol>
<organization type="scan_chain" circuit_model_name="DFFRQ" num_regions="1"/>

2
openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga
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@ -58,7 +58,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator #--explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

2
openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga
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@ -1,6 +1,6 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT}
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

3
openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh
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@ -14,3 +14,6 @@ run-task quicklogic_tests/flow_test --debug --show_thread_logs
echo -e "Testing yosys flow using custom ys script for running multi-clock quicklogic device";
run-task quicklogic_tests/counter_5clock_test --debug --show_thread_logs
run-task quicklogic_tests/sdc_controller_test --debug --show_thread_logs
echo -e "Testing yosys flow using custom ys script for adders in quicklogic device";
run-task quicklogic_tests/lut_adder_test --debug --show_thread_logs

1
openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
View File

@ -19,6 +19,7 @@ fpga_flow=yosys_vpr
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_circuit_format=eblif
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml

3
openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml Normal file
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@ -0,0 +1,3 @@
<openfpga_bitstream_setting>
<pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" source="eblif" content=".param LUT"/>
</openfpga_bitstream_setting>

41
openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf Normal file
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@ -0,0 +1,41 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml
openfpga_vpr_circuit_format=eblif
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v
[SYNTHESIS_PARAM]
bench1_top = adder_8
bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
##########################
# The output verilog of yosys is not synthesizable!!!
# Turn off verification for now
# SHOULD focus on fixing the Verilog problem and run verification at the end of the flow
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=

45
openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
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@ -125,21 +125,21 @@
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
<input name="I0" num_pins="2" equivalent="full"/>
<input name="I0" num_pins="2" equivalent="none"/>
<input name="I0i" num_pins="2" equivalent="none"/>
<input name="I1" num_pins="2" equivalent="full"/>
<input name="I1" num_pins="2" equivalent="none"/>
<input name="I1i" num_pins="2" equivalent="none"/>
<input name="I2" num_pins="2" equivalent="full"/>
<input name="I2" num_pins="2" equivalent="none"/>
<input name="I2i" num_pins="2" equivalent="none"/>
<input name="I3" num_pins="2" equivalent="full"/>
<input name="I3" num_pins="2" equivalent="none"/>
<input name="I3i" num_pins="2" equivalent="none"/>
<input name="I4" num_pins="2" equivalent="full"/>
<input name="I4" num_pins="2" equivalent="none"/>
<input name="I4i" num_pins="2" equivalent="none"/>
<input name="I5" num_pins="2" equivalent="full"/>
<input name="I5" num_pins="2" equivalent="none"/>
<input name="I5i" num_pins="2" equivalent="none"/>
<input name="I6" num_pins="2" equivalent="full"/>
<input name="I6" num_pins="2" equivalent="none"/>
<input name="I6i" num_pins="2" equivalent="none"/>
<input name="I7" num_pins="2" equivalent="full"/>
<input name="I7" num_pins="2" equivalent="none"/>
<input name="I7i" num_pins="2" equivalent="none"/>
<input name="reg_in" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
@ -333,27 +333,27 @@
</pb_type>
<!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin -->
<!-- -Due to the absence of local routing,
the 4 inputs of fracturable LUT4 are no longer equivalent,
because the 4th input can not be switched when the dual-LUT3 modes are used.
So pin equivalence should be applied to the first 3 inputs only
<!-- Due to that LUT bitstream may be overwritten by .eblif files
Pin equivalence of CLB inputs are all disabled.
This is because the hard coded bitstream in .eblif cannot be
adapted to the net swapping from VPR's routing optimization
-->
<pb_type name="clb">
<input name="I0" num_pins="2" equivalent="full"/>
<input name="I0" num_pins="2" equivalent="none"/>
<input name="I0i" num_pins="2" equivalent="none"/>
<input name="I1" num_pins="2" equivalent="full"/>
<input name="I1" num_pins="2" equivalent="none"/>
<input name="I1i" num_pins="2" equivalent="none"/>
<input name="I2" num_pins="2" equivalent="full"/>
<input name="I2" num_pins="2" equivalent="none"/>
<input name="I2i" num_pins="2" equivalent="none"/>
<input name="I3" num_pins="2" equivalent="full"/>
<input name="I3" num_pins="2" equivalent="none"/>
<input name="I3i" num_pins="2" equivalent="none"/>
<input name="I4" num_pins="2" equivalent="full"/>
<input name="I4" num_pins="2" equivalent="none"/>
<input name="I4i" num_pins="2" equivalent="none"/>
<input name="I5" num_pins="2" equivalent="full"/>
<input name="I5" num_pins="2" equivalent="none"/>
<input name="I5i" num_pins="2" equivalent="none"/>
<input name="I6" num_pins="2" equivalent="full"/>
<input name="I6" num_pins="2" equivalent="none"/>
<input name="I6i" num_pins="2" equivalent="none"/>
<input name="I7" num_pins="2" equivalent="full"/>
<input name="I7" num_pins="2" equivalent="none"/>
<input name="I7i" num_pins="2" equivalent="none"/>
<input name="reg_in" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
@ -507,9 +507,8 @@
</direct>
<direct name="direct5" input="adder_lut4.lut4_out" output="soft_adder.sumout[0:0]">
</direct>
<!-- The MUX may not be needed once we limit the number of inputs of adder_lut4 to be 2 -->
<mux name="mux1" input="soft_adder.cin soft_adder.in[2:2]" output="adder_lut4.in[2:2]">
</mux>
<direct name="direct6" input="soft_adder.in[2:2]" output="adder_lut4.in[2:2]">
</direct>
</interconnect>
</pb_type>
<interconnect>

2
yosys

@ -1 +1 @@
Subproject commit 19f4184a60b4e43f61c54236e7149a40b587d656
Subproject commit 3a9968de914973f65928b724e889b134f8a4f2ae