From db71cc8a1624a7c1d58358a48abdb5f3944dcd45 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 23 Feb 2021 16:50:58 -0700 Subject: [PATCH 01/14] [Test] Add LUT adder test using quicklogic synthesis script --- .../config/bitstream_annotation.xml | 3 ++ .../lut_adder_test/config/task.conf | 39 +++++++++++++++++++ 2 files changed, 42 insertions(+) create mode 100644 openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml create mode 100644 openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml new file mode 100644 index 000000000..735d45c23 --- /dev/null +++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml @@ -0,0 +1,3 @@ + + + diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf new file mode 100644 index 000000000..1d3f0ff86 --- /dev/null +++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf @@ -0,0 +1,39 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml +openfpga_vpr_circuit_format=eblif + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v + +[SYNTHESIS_PARAM] +########################## +# Due to the limitation in pack pattern, 8-bit adder benchmark cannot pass VPR +bench1_top = adder_8 +bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From 53df7f69e743663e4cb93cdb8fdb34679f37598c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 23 Feb 2021 16:59:46 -0700 Subject: [PATCH 02/14] [Test] Bug fix in the test case using lut adder --- .../tasks/quicklogic_tests/lut_adder_test/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf index 1d3f0ff86..b736cd5e9 100644 --- a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf @@ -32,7 +32,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/ad ########################## # Due to the limitation in pack pattern, 8-bit adder benchmark cannot pass VPR bench1_top = adder_8 -bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys +bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= From ad25944e59ddaf2f25ea194e9766de0f60536f86 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 23 Feb 2021 19:00:27 -0700 Subject: [PATCH 03/14] [Arch] Patched superLUT architecture example when trying adder8 synthesis script --- ...n_chain_nonLR_caravel_io_skywater130nm.xml | 45 +++++++++---------- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index 3d71ffff9..17e37ee04 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -125,21 +125,21 @@ - + - + - + - + - + - + - + - + @@ -333,27 +333,27 @@ - - + - + - + - + - + - + - + - + @@ -507,9 +507,8 @@ - - - + + From df7b436ac7dc2988df267bbdf619063478fc702f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 23 Feb 2021 19:01:18 -0700 Subject: [PATCH 04/14] [Tool] Patch repacker to support duplicated nets due to adder nets --- openfpga/src/repack/repack.cpp | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 91efe88c8..3611909bb 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -259,13 +259,25 @@ std::vector find_pb_route_remapped_source_pb_pin(const t_pb* pb, /* Only care the pin has the same parent port as source_pb_pin * Due to that the source_pb_pin may be swapped during routing * the pb_route is out-of-date + * + * For those parent port is defined as non-equivalent, + * the source pin and the pin recorded in the routing trace must match! + * * TODO: should update pb_route by post routing results * On the other side, the swapping can only happen between equivalent pins * in a port. So the port must match here! */ - if (source_pb_pin->port == pb->pb_route.at(pin).pb_graph_pin->port) { - pb_route_indices.push_back(pin); - } + if (PortEquivalence::FULL == source_pb_pin->port->equivalent) { + if (source_pb_pin->port == pb->pb_route.at(pin).pb_graph_pin->port) { + pb_route_indices.push_back(pin); + } + } else { + /* NOTE: INSTANCE is NOT supported! We support only NONE equivalent */ + VTR_ASSERT (PortEquivalence::NONE == source_pb_pin->port->equivalent); + if (source_pb_pin == pb->pb_route.at(pin).pb_graph_pin) { + pb_route_indices.push_back(pin); + } + } } return pb_route_indices; From a62786986b02c14dadca4513803636764a6bb523 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 23 Feb 2021 19:03:25 -0700 Subject: [PATCH 05/14] [Test] Turn off verification in adder lut test temporarily --- .../quicklogic_tests/lut_adder_test/config/task.conf | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf index b736cd5e9..e335def5a 100644 --- a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf @@ -29,11 +29,13 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_sof bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v [SYNTHESIS_PARAM] -########################## -# Due to the limitation in pack pattern, 8-bit adder benchmark cannot pass VPR bench1_top = adder_8 bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -end_flow_with_test= -vpr_fpga_verilog_formal_verification_top_netlist= +########################## +# The output verilog of yosys is not synthesizable!!! +# Turn off verification for now +# SHOULD focus on fixing the Verilog problem and run verification at the end of the flow +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= From 86a602d3812fa80bfa43ba853da1a5a25506a059 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 23 Feb 2021 19:55:07 -0700 Subject: [PATCH 06/14] [Test] Deploy new test to CI --- openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh b/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh index 776c20079..2d3bd1202 100755 --- a/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh @@ -14,3 +14,6 @@ run-task quicklogic_tests/flow_test --debug --show_thread_logs echo -e "Testing yosys flow using custom ys script for running multi-clock quicklogic device"; run-task quicklogic_tests/counter_5clock_test --debug --show_thread_logs run-task quicklogic_tests/sdc_controller_test --debug --show_thread_logs + +echo -e "Testing yosys flow using custom ys script for adders in quicklogic device"; +run-task quicklogic_tests/lut_adder_test --debug --show_thread_logs From 0ce9b66c757b25bb157a5bf8d8dfe83e4a5c53c9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 24 Feb 2021 10:09:44 -0700 Subject: [PATCH 07/14] [Arch] Add a dummy adder lut circuit model to support HDL simulation --- ...ain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index e00faa1d1..0198e5c24 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -197,6 +197,18 @@ + + + + + From 7a5dd1bc0293b56b3e8f61dc505184c6748c3857 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 24 Feb 2021 10:36:48 -0700 Subject: [PATCH 08/14] [Tools] Patch circuit library for dummy circuit models without any ports --- libopenfpga/libarchopenfpga/src/circuit_library.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp index f56b94199..537a436bc 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp @@ -1214,6 +1214,16 @@ CircuitModelId CircuitLibrary::add_model(const enum e_circuit_model_type& type) /* Build the fast look-up for circuit models */ build_model_lookup(); + /* Add a placeholder in the fast look-up for model port + * This is to avoid memory holes when a circuit model + * does not have any ports. + * As a result, the fast look-up may not even create an entry + * for this model id, which cause fast look-up abort when there is + * a query on the model + */ + model_port_lookup_.resize(model_ids_.size()); + model_port_lookup_[model_id].resize(NUM_CIRCUIT_MODEL_PORT_TYPES); + return model_id; } From 4c2a88e27f064ecb03bf05e8541265cd85974d3f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 24 Feb 2021 11:51:10 -0700 Subject: [PATCH 09/14] [Arch] Comment out yosys tech lib Verilog to see if it caused CI failed in iVerilog compilation; Now suspect that iVerilog v10.1 on CI is low; Local test with iVerilog v10.3 passed --- ...r_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 0198e5c24..d40e7bea2 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -206,9 +206,9 @@ - + From 744d87cb4edf97a026b697cc0cf49356f96f2cb9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 26 Feb 2021 09:34:52 -0700 Subject: [PATCH 10/14] [Script] Now use implicit port mapping for Verilog testbenches to avoid renaming issues --- .../bitstream_setting_example_script.openfpga | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga index ac0a1eafd..a5cbbaf16 100644 --- a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga @@ -58,7 +58,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator #--explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here From 0d82e4939cc6aeed81cfaae8a8166fa0fe5edc1f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 26 Feb 2021 09:35:40 -0700 Subject: [PATCH 11/14] [Test] Use unified quicklogic synthesis script and enable end-of-flow tests --- .../tasks/quicklogic_tests/lut_adder_test/config/task.conf | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf index e335def5a..6a5f29063 100644 --- a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf @@ -30,12 +30,12 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/ad [SYNTHESIS_PARAM] bench1_top = adder_8 -bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys +bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] ########################## # The output verilog of yosys is not synthesizable!!! # Turn off verification for now # SHOULD focus on fixing the Verilog problem and run verification at the end of the flow -#end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From ff7c9bb3c6f16293e1293a1e089a490173f86e9d Mon Sep 17 00:00:00 2001 From: Lalit Sharma Date: Sun, 28 Feb 2021 20:55:55 -0800 Subject: [PATCH 12/14] Bumping up latest yosys changes to yosys submodule --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index 19f4184a6..3a9968de9 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit 19f4184a60b4e43f61c54236e7149a40b587d656 +Subproject commit 3a9968de914973f65928b724e889b134f8a4f2ae From 0038496d9c425015513621543142134a55f7a26a Mon Sep 17 00:00:00 2001 From: Lalit Sharma Date: Sun, 28 Feb 2021 21:08:47 -0800 Subject: [PATCH 13/14] Replacing -openfpga with -family qlf_k4n8 --- openfpga_flow/misc/qlf_yosys.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/misc/qlf_yosys.ys b/openfpga_flow/misc/qlf_yosys.ys index cccd220b9..b5169287e 100644 --- a/openfpga_flow/misc/qlf_yosys.ys +++ b/openfpga_flow/misc/qlf_yosys.ys @@ -2,5 +2,5 @@ # Read verilog files ${READ_VERILOG_FILE} -synth_quicklogic -blif ${OUTPUT_BLIF} -openfpga -top ${TOP_MODULE} +synth_quicklogic -blif ${OUTPUT_BLIF} -family qlf_k4n8 -top ${TOP_MODULE} From ea4aee8cb257705e0844bd8a38d0416b844220fd Mon Sep 17 00:00:00 2001 From: Lalit Sharma Date: Sun, 28 Feb 2021 22:07:23 -0800 Subject: [PATCH 14/14] For time-being yosys script running in no_adder mode. --- openfpga_flow/misc/qlf_yosys.ys | 2 +- .../quicklogic_flow_example_script.openfpga | 2 +- openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/misc/qlf_yosys.ys b/openfpga_flow/misc/qlf_yosys.ys index b5169287e..131bddd3c 100644 --- a/openfpga_flow/misc/qlf_yosys.ys +++ b/openfpga_flow/misc/qlf_yosys.ys @@ -2,5 +2,5 @@ # Read verilog files ${READ_VERILOG_FILE} -synth_quicklogic -blif ${OUTPUT_BLIF} -family qlf_k4n8 -top ${TOP_MODULE} +synth_quicklogic -blif ${OUTPUT_BLIF} -family qlf_k4n8 -no_adder -top ${TOP_MODULE} diff --git a/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga index c9ae60b56..414fd8d47 100644 --- a/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf index 38c047162..71529c23b 100644 --- a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf @@ -19,6 +19,7 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_circuit_format=eblif [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml