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[Script] Use parameters in template yosys script supporting BRAMs

This commit is contained in:
tangxifan 2021-03-16 19:51:48 -06:00
parent cea43c2c45
commit 094b3e9b90
1 changed files with 3 additions and 3 deletions
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6
openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys
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@ -6,7 +6,7 @@
# Read verilog files
${READ_VERILOG_FILE}
# Read technology library
read_verilog -lib -specify ${OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v
read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
#########################
# Prepare for synthesis
@ -40,8 +40,8 @@ opt_clean
#########################
# Map logics to BRAMs
#########################
memory_bram -rules ${OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt
techmap -map ${OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v
memory_bram -rules ${YOSYS_BRAM_MAP_RULES}
techmap -map ${YOSYS_BRAM_MAP_VERILOG}
opt -fast -mux_undef -undriven -fine
memory_map
opt -undriven -fine