Merge branch 'master' into soft_adder_lut_support

.github/workflows/build.yml

@@ -23,6 +23,7 @@ jobs:
       # this is output as string, see https://docs.github.com/en/actions/reference/workflow-syntax-for-github-actions#jobsjob_idoutputs
       source_modified: ${{ steps.changes.outputs.status_code == '1' }}
       force_upload: false
+      sha_short: ${{ steps.changes.outputs.sha_short }}
     steps:
       - name: Checkout OpenFPGA repo
         uses: actions/checkout@v2
@@ -38,10 +39,15 @@ jobs:
           else
             echo "::set-output name=status_code::$?"
           fi
+          if [[ ${GITHUB_REF} == 'refs/heads/master' ]]; then
+            echo "Current brnach is master forcing source_modified"
+            echo "::set-output name=status_code::1"
+          fi
+          echo "::set-output name=sha_short::$(git rev-parse --short HEAD)"
   # Test the compilation compatibility
   linux_build:
     needs: change_detect
-    if: ${{ fromJSON(needs.change_detect.outputs.source_modified) || github.ref == 'refs/heads/master' }}
+    if: ${{ fromJSON(needs.change_detect.outputs.source_modified) }}
     name: ${{ matrix.config.name }}
     runs-on: ubuntu-18.04
     container: ghcr.io/lnis-uofu/openfpga-build-${{ matrix.config.cc}}
@@ -161,9 +167,8 @@ jobs:
             openfpga.sh
   docker_distribution:
     name: Build docker image for distribution
-    if: ${{ github.ref == 'refs/heads/master' || fromJSON(needs.change_detect.outputs.force_upload) }}
     runs-on: ubuntu-latest
-    needs: linux_build
+    needs: [linux_build, change_detect]
     steps:
       - name: Checkout OpenFPGA repo
         uses: actions/checkout@v2
@@ -171,9 +176,6 @@ jobs:
         uses: actions/download-artifact@v2
         with:
           name: openfpga
-      - name: Update dockerignore to add openfpga_flow
-        run: |
-          cat .dockerignore
       - name: Set up QEMU
         uses: docker/setup-qemu-action@v1
       - name: Set up Docker Buildx
@@ -189,10 +191,12 @@ jobs:
         with:
           context: .
           file: ./docker/Dockerfile.master
-          push: true
-          tags: ghcr.io/lnis-uofu/openfpga-master:latest
-  artifact_regression_tests:
-    name: Regression tests on code changes
+          push: ${{ github.ref == 'refs/heads/master' || needs.change_detect.outputs.force_upload }}
+          tags: |
+            ghcr.io/lnis-uofu/openfpga-master:latest
+            ghcr.io/lnis-uofu/openfpga-master:${{ needs.change_detect.outputs.sha_short }}
+  linux_regression_tests:
+    name: linux_regression_tests
     runs-on: ubuntu-18.04
     container: ghcr.io/lnis-uofu/openfpga-env
     needs: linux_build
@@ -237,7 +241,7 @@ jobs:
   docker_regression_tests:
     needs: change_detect
     if: ${{ !fromJSON(needs.change_detect.outputs.source_modified) }}
-    name: Regression tests against master artifacts
+    name: docker_regression_tests
     runs-on: ubuntu-18.04
     container: ghcr.io/lnis-uofu/openfpga-master:latest
     strategy:

docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst

@@ -49,7 +49,8 @@ write_openfpga_simulation_setting
 
   .. option:: --file <string> or -f <string>
      
-    Specify the file name. For example, ``--file auto_simulation_setting_echo.xml`` 
+    Specify the file name. For example, ``--file auto_simulation_setting_echo.xml``.
+    See details about file format at :ref:`simulation_setting`.
 
   .. option:: --verbose
 
@@ -62,7 +63,8 @@ link_openfpga_arch
 
   .. option:: --activity_file <string>
 
-    Specify the signal activity file. For example, ``--activity_file counter.act``
+    Specify the signal activity file. For example, ``--activity_file counter.act``.
+    This is required when users wants OpenFPGA to automatically find the number of clocks in simulations. See details at :ref:`simulation_setting`.
 
   .. option:: --sort_gsb_chan_node_in_edges
 

openfpga/src/annotation/annotate_simulation_setting.cpp

@@ -237,6 +237,12 @@ int annotate_simulation_setting(const AtomContext& atom_ctx,
      */
     VTR_LOG("User specified the number of operating clock cycles to be inferred from signal activities\n");
 
+    /* Error out if net activity is not defined */ 
+    if (true == net_activity.empty()) {
+      VTR_LOG_ERROR("Signal activities are not defined!\nPlease check if activity file is given and properly generated!\n");
+      return CMD_EXEC_FATAL_ERROR;
+    }
+
     /* Use a fixed simulation window size now. TODO: this could be specified by users */
     size_t num_clock_cycles = recommend_num_sim_clock_cycle(atom_ctx,
                                                             net_activity, 

openfpga/src/base/openfpga_context.h

@@ -67,7 +67,6 @@ class OpenfpgaContext : public Context  {
     const openfpga::FabricBitstream& fabric_bitstream() const { return fabric_bitstream_; }
     const openfpga::IoLocationMap& io_location_map() const { return io_location_map_; }
     const openfpga::FabricGlobalPortInfo& fabric_global_port_info() const { return fabric_global_port_info_; }
-    const std::unordered_map<AtomNetId, t_net_power>& net_activity() const { return net_activity_; }
     const openfpga::NetlistManager& verilog_netlists() const { return verilog_netlists_; }
     const openfpga::NetlistManager& spice_netlists() const { return spice_netlists_; }
   public:  /* Public mutators */
@@ -88,7 +87,6 @@ class OpenfpgaContext : public Context  {
     openfpga::FabricBitstream& mutable_fabric_bitstream() { return fabric_bitstream_; }
     openfpga::IoLocationMap& mutable_io_location_map() { return io_location_map_; }
     openfpga::FabricGlobalPortInfo& mutable_fabric_global_port_info() { return fabric_global_port_info_; }
-    std::unordered_map<AtomNetId, t_net_power>& mutable_net_activity() { return net_activity_; }
     openfpga::NetlistManager& mutable_verilog_netlists() { return verilog_netlists_; }
     openfpga::NetlistManager& mutable_spice_netlists() { return spice_netlists_; }
   private: /* Internal data */
@@ -138,9 +136,6 @@ class OpenfpgaContext : public Context  {
     openfpga::NetlistManager verilog_netlists_;
     openfpga::NetlistManager spice_netlists_;
 
-    /* Net activities of users' implementation */
-    std::unordered_map<AtomNetId, t_net_power> net_activity_; 
- 
     /* Flow status */
     openfpga::FlowManager flow_manager_;
 };

openfpga/src/base/openfpga_link_arch.cpp

@@ -148,8 +148,11 @@ int link_arch(OpenfpgaContext& openfpga_ctx,
    *   should be inferred from FPGA implmentation
    * - When FPGA-SPICE is enabled
    */
-  openfpga_ctx.mutable_net_activity() = read_activity(g_vpr_ctx.atom().nlist,
-                                                      cmd_context.option_value(cmd, opt_activity_file).c_str());
+  std::unordered_map<AtomNetId, t_net_power> net_activity;
+  if (true == cmd_context.option_enable(cmd, opt_activity_file)) {
+    net_activity = read_activity(g_vpr_ctx.atom().nlist,
+                                 cmd_context.option_value(cmd, opt_activity_file).c_str());
+  }
 
   /* TODO: Annotate the number of clock cycles and clock frequency by following VPR results
    * We SHOULD create a new simulation setting for OpenFPGA use only
@@ -160,7 +163,7 @@ int link_arch(OpenfpgaContext& openfpga_ctx,
    */
   //openfpga_ctx.mutable_simulation_setting() = openfpga_ctx.mutable_arch().sim_setting;
   if (CMD_EXEC_FATAL_ERROR == annotate_simulation_setting(g_vpr_ctx.atom(),
-                                                          openfpga_ctx.net_activity(),
+                                                          net_activity,
                                                           openfpga_ctx.mutable_simulation_setting())) {
     return CMD_EXEC_FATAL_ERROR;
   }

openfpga/src/base/openfpga_setup_command.cpp

@@ -125,7 +125,7 @@ ShellCommandId add_openfpga_link_arch_command(openfpga::Shell<OpenfpgaContext>&
   Command shell_cmd("link_openfpga_arch");
 
   /* Add an option '--activity_file'*/
-  CommandOptionId opt_act_file = shell_cmd.add_option("activity_file", true, "file path to the signal activity");
+  CommandOptionId opt_act_file = shell_cmd.add_option("activity_file", false, "file path to the signal activity");
   shell_cmd.set_option_require_value(opt_act_file, openfpga::OPT_STRING);
 
   /* Add an option '--sort_gsb_chan_node_in_edges'*/

openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga

@@ -12,7 +12,11 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
 
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
-link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+# Note: no need to assign activity file when you used a fixed number 
+#       of clock cycles in simulation settings
+#       Also, ACE2 does not support multiple clocks
+#       Therefore, activity file is not recommended for multi-clock fabric/implementations
+link_openfpga_arch --sort_gsb_chan_node_in_edges
 
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml