Made activity file independent of power option
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eaf8ecee86
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@ -234,10 +234,11 @@ def main():
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if (args.fpga_flow == "yosys_vpr"):
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logger.info('Running "yosys_vpr" Flow')
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run_yosys_with_abc()
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# TODO Make it optional if activity file is provided
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run_ace2()
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run_pro_blif_3arg()
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if args.power:
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run_ace2()
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run_pro_blif_3arg()
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run_rewrite_verilog()
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run_rewrite_verilog()
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if (args.fpga_flow == "vpr_blif"):
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collect_files_for_vpr()
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# if (args.fpga_flow == "vtr"):
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@ -642,13 +643,13 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
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"--place_file", args.top_module+"_vpr.place",
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"--route_file", args.top_module+"_vpr.route",
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"--full_stats", "--nodisp",
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"--activity_file", args.top_module+"_ace_out.act",
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]
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if route_only:
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command += ["--route"]
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# Power options
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if args.power:
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command += ["--power",
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"--activity_file", args.top_module+"_ace_out.act",
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"--tech_properties", args.power_tech]
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# packer options
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if args.vpr_timing_pack_off:
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@ -700,7 +701,7 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
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command += ["--fpga_spice_testbench_load_extraction", "off"]
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# FPGA Verilog options
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if (args.power and args.vpr_fpga_verilog):
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if args.vpr_fpga_verilog:
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command += ["--fpga_verilog"]
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if args.vpr_fpga_verilog_dir:
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command += ["--fpga_verilog_dir", args.vpr_fpga_verilog_dir]
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