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try to add aib test case. bug found

This commit is contained in:
tangxifan 2020-04-12 14:54:45 -06:00
parent 28cb412359
commit da5af8f0e0
4 changed files with 56 additions and 3 deletions
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19
openfpga_flow/VerilogNetlists/aib.v Normal file
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@ -0,0 +1,19 @@
//-----------------------------------------------------
// Design Name : AIB interface
// File Name : aib.v
// Function : A wrapper for AIB interface
// Coder : Xifan Tang
//-----------------------------------------------------
module aib (
input tx_clk,
input rx_clk,
inout[0:79] pad,
input[0:79] tx_data,
output[0:79] rx_data);
// May add the logic function of a real AIB
// Refer to the offical AIB github
// https://github.com/intel/aib-phy-hardware
endmodule

4
openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
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@ -225,7 +225,7 @@
<!-- Physical descriptions begin -->
<layout tileable="true" through_channel="false">
<!--auto_layout aspect_ratio="1.0"-->
<fixed_layout name="4x4" width="7" height="6">
<fixed_layout name="3x4" width="5" height="6">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="10"/>
<corners type="EMPTY" priority="101"/>
@ -235,7 +235,7 @@
<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
<!-- Single instance of an AIB interface -->
<single type="aib" x="6" y="1" priority="20"/>
<single type="aib" x="4" y="1" priority="20"/>
</fixed_layout>
<!-- /auto_layout -->
</layout>

2
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
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@ -189,7 +189,7 @@
<port type="output" prefix="sumout" size="1"/>
<port type="output" prefix="cout" size="1"/>
</circuit_model>
<circuit_model type="hard_logic" name="dpram_512x32" prefix="dpram_512x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpsram.v">
<circuit_model type="hard_logic" name="dpram_512x32" prefix="dpram_512x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram16k.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>

34
openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf Normal file
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
[SYNTHESIS_PARAM]
bench0_top = top
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
bench0_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=