[OpenFPGA Flow] Add Verilog HDL for configurable latch with active-low reset

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tangxifan 2020-09-23 17:19:02 -06:00
parent 5c62bafa7f
commit b242ab79bd
1 changed files with 39 additions and 0 deletions

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//-----------------------------------------------------
// Design Name : config_latch
// File Name : config_latch.v
// Function : A Configurable Latch where data storage
// can be updated at rising clock edge
// when wl is enabled
// Reset is active low
// Coder : Xifan TANG
//-----------------------------------------------------
module config_latch (
input resetb, // Reset input
input clk, // Clock Input
input wl, // Data Enable
input bl, // Data Input
output Q, // Q output
output Qb // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge clk or posedge resetb) begin
if (~resetb) begin
q_reg <= 1'b0;
end else if (1'b1 == wl) begin
q_reg <= bl;
end
end
`ifndef ENABLE_FORMAL_VERIFICATION
// Wire q_reg to Q
assign Q = q_reg;
assign Qb = ~q_reg;
`else
assign Q = 1'bZ;
assign Qb = !Q;
`endif
endmodule