From b242ab79bd4125bd5cb2742c25b7a373a5814901 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 23 Sep 2020 17:19:02 -0600
Subject: [PATCH] [OpenFPGA Flow] Add Verilog HDL for configurable latch with
 active-low reset

---
 .../VerilogNetlists/config_latch_neg_rst.v    | 39 +++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 openfpga_flow/VerilogNetlists/config_latch_neg_rst.v

diff --git a/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v b/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v
new file mode 100644
index 000000000..917bf88ce
--- /dev/null
+++ b/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v
@@ -0,0 +1,39 @@
+//-----------------------------------------------------
+// Design Name : config_latch
+// File Name   : config_latch.v
+// Function    : A Configurable Latch where data storage
+//               can be updated at rising clock edge 
+//               when wl is enabled
+//               Reset is active low
+// Coder       : Xifan TANG
+//-----------------------------------------------------
+module config_latch (
+  input resetb, // Reset input
+  input clk, // Clock Input
+  input wl, // Data Enable
+  input bl, // Data Input
+  output Q, // Q output
+  output Qb // Q output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge clk or posedge resetb) begin
+  if (~resetb) begin
+    q_reg <= 1'b0;
+  end else if (1'b1 == wl) begin
+    q_reg <= bl;
+  end
+end
+
+`ifndef ENABLE_FORMAL_VERIFICATION
+// Wire q_reg to Q
+assign Q = q_reg;
+assign Qb = ~q_reg;
+`else
+assign Q = 1'bZ;
+assign Qb = !Q;
+`endif
+
+endmodule