add notes about debugging the aib FPGA
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@ -17,6 +17,17 @@ timeout_each_job = 20*60
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fpga_flow=vpr_blif
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
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#####################################
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# Debugging status
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# Fail in the following cases
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# - tileable routing is used
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# - vpr routing is used
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# - compressed routing is enabled/disabled
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# - duplicated pin is enabled/disabled
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#
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# Therefore, this could be a bug in the VPR
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####################################
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
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