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Adding heterogeneous synthesis requirements

This commit is contained in:
AurelienUoU 2019-12-03 16:09:26 -07:00
parent 32176eb352
commit 09fd2afa9c
6 changed files with 351 additions and 4 deletions
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8
openfpga_flow/VerilogNetlists/dpram.v
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@ -1,7 +1,7 @@
//-----------------------------------------------------
// Design Name : dual_port_ram
// File Name : memory_wrapper.v
// Function : Dual port RAM 64x2048
// File Name : dpram.v
// Function : Dual port RAM 32x1024
// Coder : Aurelien
//-----------------------------------------------------
@ -41,13 +41,13 @@ module dual_port_sram (
assign d_out = internal;
always @(negedge wclk) begin
always @(posedge wclk) begin
if(wen) begin
ram[waddr] <= data_in;
end
end
always @(negedge rclk) begin
always @(posedge rclk) begin
if(ren) begin
internal <= ram[raddr];
end

36
openfpga_flow/misc/OpenFPGA_lib/brams.txt Normal file
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@ -0,0 +1,36 @@
bram $__MY_DPRAM
init 0
abits 10
dbits 32
groups 2
ports 1 1
wrmode 1 0
enable 1 1
transp 0 0
clocks 1 1
clkpol 1 1
endbram
bram $__MY_SPRAM
init 0
abits 10
dbits 32
groups 2
ports 1 1
wrmode 1 0
enable 1 0
transp 0 0
clocks 1 1
clkpol 1 1
endbram
match $__MY_DPRAM
min efficiency 0
make_transp
or_next_if_better
endmatch
match $__MY_SPRAM
min efficiency 0
make_transp
endmatch

44
openfpga_flow/misc/OpenFPGA_lib/brams_map.v Normal file
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@ -0,0 +1,44 @@
module $__MY_DPRAM (
output[31:0] B1DATA,
input CLK1,
input[9:0] B1ADDR,
input[9:0] A1ADDR,
input[31:0] A1DATA,
input A1EN,
input B1EN );
generate
dpram #() _TECHMAP_REPLACE_ (
.clk (CLK1),
.wen (A1EN),
.waddr (A1ADDR),
.d_in (A1DATA),
.ren (B1EN),
.raddr (B1ADDR),
.d_out (B1DATA) );
endgenerate
endmodule
module $__MY_SPRAM (
output[31:0] B1DATA,
input CLK1,
input[9:0] B1ADDR,
input[9:0] A1ADDR,
input[31:0] A1DATA,
input A1EN );
generate
dpram #() _TECHMAP_REPLACE_ (
.clk (CLK1),
.wen (A1EN),
.waddr (A1ADDR),
.d_in (A1DATA),
.ren (1'b1),
.raddr (A1ADDR),
.d_out (B1DATA) );
endgenerate
endmodule

62
openfpga_flow/misc/OpenFPGA_lib/cells_sim.v Normal file
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@ -0,0 +1,62 @@
module dpram (
input clk,
input wen,
input ren,
input[9:0] waddr,
input[9:0] raddr,
input[31:0] d_in,
output[31:0] d_out );
dual_port_sram memory_0 (
.wclk (clk),
.wen (wen),
.waddr (waddr),
.data_in (d_in),
.rclk (clk),
.ren (ren),
.raddr (raddr),
.d_out (d_out) );
endmodule
module dual_port_sram (
input wclk,
input wen,
input[9:0] waddr,
input[31:0] data_in,
input rclk,
input ren,
input[9:0] raddr,
output[31:0] d_out );
reg[31:0] ram[1023:0];
reg[31:0] internal;
assign d_out = internal;
always @(posedge wclk) begin
if(wen) begin
ram[waddr] <= data_in;
end
end
always @(posedge rclk) begin
if(ren) begin
internal <= ram[raddr];
end
end
endmodule
module adder(
input cin,
input a,
input b,
output cout,
output sumout );
assign sumout = a ^ b ^ cin;
assign cout = (a & b) | ((a | b) & cin);
endmodule

164
openfpga_flow/misc/OpenFPGA_lib/fpga_techmap.v Normal file
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@ -0,0 +1,164 @@
//////////////////////////
// arithmetic //
//////////////////////////
module \$alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH:0] X, Y;
input CI, BI;
output [Y_WIDTH:0] CO;
wire [Y_WIDTH-1:0] AA, BB;
wire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean";
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B);
end else begin:BLOCK2
assign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B);
end
endgenerate
wire [Y_WIDTH: 0 ] CARRY;
assign CARRY[0] = CI;
genvar i;
generate for (i = 0; i < Y_WIDTH - 1; i = i+1) begin:gen3
adder my_adder (
.cin (CARRY[i]),
.cout (CARRY[i+1]),
.a (AA[i]),
.b (BB[i]),
.sumout (Y[i])
);
end endgenerate
generate if ((Y_WIDTH -1) % 20 == 0) begin:gen4
assign Y[Y_WIDTH-1] = CARRY[Y_WIDTH-1];
end else begin:gen5
adder my_adder (
.cin (CARRY[Y_WIDTH - 1]),
.cout (CARRY[Y_WIDTH]),
.a (1'b0),
.b (1'b0),
.sumout (Y[Y_WIDTH -1])
);
end
endgenerate
endmodule
//---------------------------------------------------------
module \$fa (A, B, C, X, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
input C;
output [Y_WIDTH:0] X, Y;
wire [Y_WIDTH-1:0] AA, BB;
wire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean";
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign AA = $signed(A), BB = $signed(B);
end else begin:BLOCK2
assign AA = $unsigned(A), BB = $unsigned(B);
end
endgenerate
wire [Y_WIDTH: 0 ] CARRY;
assign CARRY[0] = C;
genvar i;
generate for (i = 0; i < Y_WIDTH - 1; i = i+1) begin:gen3
adder my_adder (
.cin (CARRY[i]),
.cout (CARRY[i+1]),
.a (AA[i]),
.b (BB[i]),
.sumout (Y[i])
);
end endgenerate
generate if ((Y_WIDTH -1) % 20 == 0) begin:gen4
assign Y[Y_WIDTH-1] = CARRY[Y_WIDTH-1];
end else begin:gen5
adder my_adder (
.cin (CARRY[Y_WIDTH - 1]),
.cout (CARRY[Y_WIDTH]),
.a (1'b0),
.b (1'b0),
.sumout (Y[Y_WIDTH -1])
);
end
endgenerate
endmodule
//---------------------------------------------------------
module \$add (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH:0] Y;
wire [Y_WIDTH-1:0] AA, BB;
wire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean";
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign AA = $signed(A), BB = $signed(B);
end else begin:BLOCK2
assign AA = $unsigned(A), BB = $unsigned(B);
end
endgenerate
wire [Y_WIDTH: 0 ] CARRY;
assign CARRY[0] = 1'b0;
genvar i;
generate for (i = 0; i < Y_WIDTH - 1; i = i+1) begin:gen3
adder my_adder (
.cin (CARRY[i]),
.cout (CARRY[i+1]),
.a (AA[i]),
.b (BB[i]),
.sumout (Y[i])
);
end endgenerate
generate if ((Y_WIDTH -1) % 20 == 0) begin:gen4
assign Y[Y_WIDTH-1] = CARRY[Y_WIDTH-1];
end else begin:gen5
adder my_adder (
.cin (CARRY[Y_WIDTH - 1]),
.cout (CARRY[Y_WIDTH]),
.a (1'b0),
.b (1'b0),
.sumout (Y[Y_WIDTH -1])
);
end
endgenerate
endmodule

41
openfpga_flow/misc/yosys_bram_adder_template.ys Normal file
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@ -0,0 +1,41 @@
# Yosys synthesis script for alu4
# read Verilog
read_verilog /full_path/design.v #can be repeated if project has many files
read_verilog -lib /full_path/cells_sim.v # file we provide
hierarchy -check -top top_module
proc
flatten
tribuf -logic
synth -run coarse
opt -fast
memory -nomap
opt_clean
memory_bram -rules /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/brams.txt
techmap -map /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/brams_map.v
opt -fast -mux_undef -undriven -fine
memory_map
# Technology mapping
#proc
techmap -D NO_LUT -map /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/fpga_techmap.v -map +/adff2dff.v
# Synthesis
synth -top top_module -flatten -run fine
clean
# LUT mapping
abc -lut 6
# Check
synth -run check
# Clean and output blif
opt_clean -purge
write_blif design.blif
write_verilog design.v