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OpenFPGA
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Update documentation about cmake version and graphical interface

This commit is contained in:
AurelienUoU 2020-01-22 20:46:49 -07:00
parent 07ad32241a
commit 85c9f26a9f
9 changed files with 31 additions and 111 deletions
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3
README.md
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@ -16,9 +16,10 @@ mkdir build && cd build # Create a folder named build in the OpenPFGA
cmake .. -DCMAKE_BUILD_TYPE=debug # Create a Makefile in this folder using cmake
make # Compile the tool and its dependencies
```
*cmake3.12 is required to use graphical interface*
We currently target OpenFPGA for:
1. Ubuntu 16.04
1. Ubuntu 18.04
2. Red Hat 7.5
3. MacOS Mojave 10.14.4

34
fpga_flow/configs/tutorial/tuto.conf
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@ -1,27 +1,27 @@
# Standard Configuration Example
[dir_path]
script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/
benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/MCNC
yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys
odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe
cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit
abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc
abc_mccl_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc
abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc
mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1
m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net
mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2
vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr
rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results_tutorial
ace_path = OPENFPGAPATHKEYWORD/ace2/ace
script_base = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/scripts/
benchmark_dir = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/benchmarks/Verilog/MCNC
yosys_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/yosys/yosys
odin2_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/odin2.exe
cirkit_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/cirkit
abc_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/yosys/yosys-abc
abc_mccl_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/abc_with_bb_support/abc
abc_with_bb_support_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/abc_with_bb_support/abc
mpack1_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/mpack1
m2net_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/m2net
mpack2_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/mpack2
vpr_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/vpr
rpt_dir = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/results_tutorial
ace_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/ace2/ace
[flow_conf]
flow_type = yosys_vpr #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr
vpr_arch = OPENFPGAPATHKEYWORD/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml
vpr_arch = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml
mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
m2net_conf = OPENFPGAPATHKEYWORD/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
m2net_conf = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
mpack2_arch = K6_pattern7_I24.arch
power_tech_xml = OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
power_tech_xml = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
[csv_tags]
mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:

2
fpga_flow/scripts/convert_blif.pl
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@ -11,7 +11,7 @@ my ($fname,$frpt);
sub print_usage()
{
print "VPR accepts a certain format of blif so this script checks the latches and corrects them if needed\n"
print "VPR accepts a certain format of blif so this script checks the latches and corrects them if needed\n";
print "Usage:\n";
print " perl <script_name.pl> [-options]\n";
print " Options:(Mandatory!)\n";

20
openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml
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@ -421,12 +421,12 @@
<port type="output" prefix="sumout" size="1"/>
<port type="output" prefix="cout" size="1"/>
</circuit_model>
<circuit_model type="hard_logic" name="dual_port_ram_32x512" prefix="dual_port_ram_32x512" dump_explicit_port_map="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/spram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram.v">
<circuit_model type="hard_logic" name="dpram" prefix="dual_port_ram_32x512" dump_explicit_port_map="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/spram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="buf1"/>
<output_buffer exist="on" circuit_model_name="buf1"/>
<port type="input" prefix="waddr" size="9"/>
<port type="input" prefix="raddr" size="9"/>
<port type="input" prefix="waddr" size="10"/>
<port type="input" prefix="raddr" size="10"/>
<port type="input" prefix="d_in" size="32"/>
<port type="input" prefix="wen" size="1"/>
<port type="input" prefix="ren" size="1"/>
@ -615,8 +615,8 @@
<pb_type name="memory_dp" height="2" area="548000">
<input name="waddr" num_pins="9" equivalent="false"/>
<input name="raddr" num_pins="9" equivalent="false"/>
<input name="waddr" num_pins="10" equivalent="false"/>
<input name="raddr" num_pins="10" equivalent="false"/>
<input name="d_in" num_pins="32" equivalent="false"/>
<input name="wen" num_pins="1"/>
<input name="ren" num_pins="1"/>
@ -624,16 +624,16 @@
<clock name="clk" num_pins="1"/>
<pb_type name="memory" num_pb="1">
<input name="waddr" num_pins="9"/>
<input name="raddr" num_pins="9"/>
<input name="waddr" num_pins="10"/>
<input name="raddr" num_pins="10"/>
<input name="d_in" num_pins="32"/>
<input name="wen" num_pins="1"/>
<input name="ren" num_pins="1"/>
<output name="d_out" num_pins="32"/>
<clock name="clk" num_pins="1"/>
<pb_type name="dpram" num_pb="1" blif_model=".subckt dual_port_ram_32x512" circuit_model_name="dual_port_ram_32x512">
<input name="waddr" num_pins="9" port_class="address"/>
<input name="raddr" num_pins="9" port_class="address"/>
<pb_type name="dpram" num_pb="1" blif_model=".subckt dual_port_ram_32x512" circuit_model_name="dpram">
<input name="waddr" num_pins="10" port_class="address"/>
<input name="raddr" num_pins="10" port_class="address"/>
<input name="d_in" num_pins="32" port_class="data_in"/>
<input name="wen" num_pins="1" port_class="write_en"/>
<input name="ren" num_pins="1" port_class="read_en"/>

2
openfpga_flow/tasks/basic_flow/config/golden_results.txt
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@ -1,2 +0,0 @@
arch circuit vpr_revision vpr_status error num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height num_clb num_io num_outputs num_memories num_mult placed_wirelength_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration crit_path_routed_wirelength crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile crit_path_routing_area_total crit_path_routing_area_per_tile odin_synth_time abc_synth_time abc_cec_time abc_sec_time ace_time pack_time place_time min_chan_width_route_time crit_path_route_time vtr_flow_elapsed_time max_vpr_mem max_odin_mem max_abc_mem
k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v 30d086154 success 419 549 298 249 10 10 19 99 130 1 0 2262 2.74023 -250.655 -2.74023 42 2555 15 2250 12 3.5255 -318.677 -3.5255 0 0 3.92691e+06 1.57199e+06 236681. 2366.81 297605. 2976.05 0.03 0.00 -1 -1 -1 0.15 0.27 0.64 0.06 1.70 -1 -1 -1

39
openfpga_flow/tasks/basic_flow/config/task.conf
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@ -1,39 +0,0 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml
power_analysis = true
spice_output=false
verilog_output=false
timeout_each_job = 20*60
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/elliptic/elliptic.v
[SYNTHESIS_PARAM]
bench0_top = s298
bench1_top = elliptic
[SCRIPT_PARAM_1]
min_route_chan_width=1.3
[SCRIPT_PARAM_2]
min_route_chan_width=1.8
[POST_RUN]
# Not Implemented yet
# Parse info and how to parse
parse_file=vpr_standard.txt
# Pass requirements
pass_requirements_file=pass_requirements.txt

2
openfpga_flow/tasks/regression/regression_quick/config/golden_results.txt
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@ -1,2 +0,0 @@
arch circuit vpr_revision vpr_status error num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height num_clb num_io num_outputs num_memories num_mult placed_wirelength_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration crit_path_routed_wirelength crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile crit_path_routing_area_total crit_path_routing_area_per_tile odin_synth_time abc_synth_time abc_cec_time abc_sec_time ace_time pack_time place_time min_chan_width_route_time crit_path_route_time vtr_flow_elapsed_time max_vpr_mem max_odin_mem max_abc_mem
k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v 30d086154 success 419 549 298 249 10 10 19 99 130 1 0 2262 2.74023 -250.655 -2.74023 42 2555 15 2250 12 3.5255 -318.677 -3.5255 0 0 3.92691e+06 1.57199e+06 236681. 2366.81 297605. 2976.05 0.03 0.00 -1 -1 -1 0.15 0.27 0.64 0.06 1.70 -1 -1 -1

38
openfpga_flow/tasks/regression/regression_quick/config/task.conf
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@ -1,38 +0,0 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_22nm/22nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/alu4/alu4.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/tseng/tseng.v
[SYNTHESIS_PARAM]
bench0_top = s298
bench1_top = alu4
bench2_top = tseng
[SCRIPT_PARAM]
min_route_chan_width=1.3
end_flow_with_test=
vpr_fpga_verilog_include_icarus_simulator=
vpr_fpga_verilog_formal_verification_top_netlist=
vpr_fpga_verilog_include_timing=
vpr_fpga_verilog_include_signal_init=
vpr_fpga_verilog_print_autocheck_top_testbench=
[POST_RUN]

2
tutorials/building.md
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@ -7,7 +7,7 @@ OpenFPGA requires all the following dependencies:
- bash
- bison
- build-essential
- cmake (version 3.X at least)
- cmake (version 3.12 for graphical interface or at least 3.X)
- ctags
- curl
- doxygen