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update arch to support reset signal for SRAm

This commit is contained in:
tangxifan 2020-05-31 13:26:55 -06:00
parent 8267dad8ef
commit baa2c6b7ef
2 changed files with 7 additions and 10 deletions
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16
openfpga_flow/VerilogNetlists/sram.v
View File

@ -6,10 +6,11 @@
// Coder : Xifan TANG
//-----------------------------------------------------
module sram_blwl(
input reset, // Word line control signal
input wl, // Word line control signal
input bl, // Bit line control signal
output out, // Data output
output outb, // Data output
output outb // Data output
);
//----- local variable need to be registered
@ -18,23 +19,18 @@ output outb, // Data output
//----- when wl is enabled, we can read in data from bl
always @(bl, wl)
begin
if (1'b1 == reset) begin
data <= 1'b0;
end else if ((1'b1 == bl)&&(1'b1 == wl)) begin
//----- Cases to program internal memory bit
//----- case 1: bl = 1, wl = 1, a -> 0
if ((1'b1 == bl)&&(1'b1 == wl)) begin
data <= 1'b1;
end
end else if ((1'b0 == bl)&&(1'b1 == wl)) begin
//----- case 2: bl = 0, wl = 1, a -> 0
if ((1'b0 == bl)&&(1'b1 == wl)) begin
data <= 1'b0;
end
end
`ifdef ENABLE_SIGNAL_INITIALIZATION
initial begin
$deposit(data, $random);
end
`endif
`ifndef ENABLE_FORMAL_VERIFICATION
// Wire q_reg to Q
assign out = data;

1
openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
View File

@ -146,6 +146,7 @@
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" size="1"/>
<port type="wl" prefix="wl" size="1"/>
<port type="output" prefix="out" size="1"/>