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add decoder support for Z signals

This commit is contained in:
tangxifan 2020-05-31 13:12:00 -06:00
parent aac2e8c805
commit 8267dad8ef
2 changed files with 4 additions and 2 deletions
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1
libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
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@ -508,7 +508,6 @@ bool check_circuit_library(const CircuitLibrary& circuit_lib) {
/* 6. SRAM must have at least an input and an output ports*/
std::vector<enum e_circuit_model_port_type> sram_port_types_required;
sram_port_types_required.push_back(CIRCUIT_MODEL_PORT_INPUT);
sram_port_types_required.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
num_err += check_circuit_model_port_required(circuit_lib, CIRCUIT_MODEL_SRAM, sram_port_types_required);

5
openfpga/src/fpga_verilog/verilog_decoders.cpp
View File

@ -484,7 +484,10 @@ void print_verilog_arch_decoder_with_data_in_module(std::fstream& fp,
fp << ") begin" << std::endl;
fp << "\tif (" << generate_verilog_port(VERILOG_PORT_CONKT, enable_port) << " == 1'b1) begin" << std::endl;
fp << "\t\t" << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size, data_size));
fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, data_port);
fp << " = ";
std::string high_res_str = "{" + std::to_string(data_port.get_width()) + "{1'bz}}";
fp << high_res_str;
fp << ";" << std::endl;
fp << "\t\t" << "case (" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl;
/* Create a string for addr and data */