From baa2c6b7ef16a7ad054a74a19740a011fe2f570c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 31 May 2020 13:26:55 -0600
Subject: [PATCH] update arch to support reset signal for SRAm

---
 openfpga_flow/VerilogNetlists/sram.v             | 16 ++++++----------
 .../openfpga_arch/k4_N4_40nm_bank_openfpga.xml   |  1 +
 2 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/openfpga_flow/VerilogNetlists/sram.v b/openfpga_flow/VerilogNetlists/sram.v
index 8b2c6c2d6..c27dbeebe 100644
--- a/openfpga_flow/VerilogNetlists/sram.v
+++ b/openfpga_flow/VerilogNetlists/sram.v
@@ -6,10 +6,11 @@
 // Coder       : Xifan TANG
 //-----------------------------------------------------
 module sram_blwl(
+input reset, // Word line control signal
 input wl, // Word line control signal
 input bl, // Bit line control signal
 output out, // Data output
-output outb, // Data output
+output outb // Data output
 );
 
   //----- local variable need to be registered
@@ -18,23 +19,18 @@ output outb, // Data output
   //----- when wl is enabled, we can read in data from bl
   always @(bl, wl) 
   begin
+    if (1'b1 == reset) begin 
+      data <= 1'b0;
+    end else if ((1'b1 == bl)&&(1'b1 == wl)) begin
     //----- Cases to program internal memory bit 
     //----- case 1: bl = 1, wl = 1, a -> 0
-    if ((1'b1 == bl)&&(1'b1 == wl)) begin
       data <= 1'b1;
-    end 
+    end else if ((1'b0 == bl)&&(1'b1 == wl)) begin
     //----- case 2: bl = 0, wl = 1, a -> 0
-    if ((1'b0 == bl)&&(1'b1 == wl)) begin
      data <= 1'b0;
     end 
   end
 
-`ifdef ENABLE_SIGNAL_INITIALIZATION
-   initial begin
-     $deposit(data, $random);
-   end
-`endif
-
 `ifndef ENABLE_FORMAL_VERIFICATION
     // Wire q_reg to Q
     assign out = data;
diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
index 487cd91e0..fe7d3f1b8 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
@@ -146,6 +146,7 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="bl" prefix="bl" size="1"/>
        <port type="wl" prefix="wl" size="1"/>
        <port type="output" prefix="out" size="1"/>