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Adding this testcase to CI script. Also adding an option in ys script for synthesis to use openfpga compliant FF

This commit is contained in:
Lalit Sharma 2020-12-16 04:19:56 -08:00
parent 891e2f8aa3
commit 1f994319fd
2 changed files with 4 additions and 1 deletions
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3
.github/workflows/basic_reg_test.sh vendored
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@ -108,3 +108,6 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/til
echo -e "Testing global port definition from tiles";
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_reset --debug --show_thread_logs
echo -e "Testing yosys flow using custom ys script for running quicklogic device";
python3 openfpga_flow/scripts/run_fpga_task.py quicklogic_tests/flow_test --debug --show_thread_logs

2
openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
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@ -2,5 +2,5 @@
# Read verilog files
${READ_VERILOG_FILE}
synth_quicklogic -blif ${TOP_MODULE}.eblif -family ap3 -vpr -top ${TOP_MODULE}
synth_quicklogic -blif ${TOP_MODULE}.eblif -family ap3 -vpr -openfpga -top ${TOP_MODULE}