diff --git a/.github/workflows/basic_reg_test.sh b/.github/workflows/basic_reg_test.sh
index 02d5da8db..3e67023e3 100755
--- a/.github/workflows/basic_reg_test.sh
+++ b/.github/workflows/basic_reg_test.sh
@@ -108,3 +108,6 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/til
 echo -e "Testing global port definition from tiles";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_reset --debug --show_thread_logs
+
+echo -e "Testing yosys flow using custom ys script for running quicklogic device";
+python3 openfpga_flow/scripts/run_fpga_task.py quicklogic_tests/flow_test --debug --show_thread_logs
diff --git a/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys b/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
index b8f65ba92..ce527daa0 100644
--- a/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
+++ b/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
@@ -2,5 +2,5 @@
 # Read verilog files
 ${READ_VERILOG_FILE}
 
-synth_quicklogic -blif ${TOP_MODULE}.eblif -family ap3 -vpr -top ${TOP_MODULE}
+synth_quicklogic -blif ${TOP_MODULE}.eblif -family ap3 -vpr -openfpga -top ${TOP_MODULE}