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[Test] Adapt bitstream annotatin file to parser's requirement

This commit is contained in:
tangxifan 2021-02-01 17:38:36 -07:00
parent 280c9620aa
commit 04594cb7ab
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml
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@ -1,3 +1,3 @@
<bitstream_annotations>
<openfpga_bitstream_setting>
<pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" source="eblif" content=".param LUT"/>
</bitstream_annotations>
</openfpga_bitstream_setting>