From 04594cb7abdd94290c2e0be46670fee20767a500 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 1 Feb 2021 17:38:36 -0700
Subject: [PATCH] [Test] Adapt bitstream annotatin file to parser's requirement

---
 .../adder/soft_adder/config/bitstream_annotation.xml          | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml
index efbfcae62..735d45c23 100644
--- a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml
+++ b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml
@@ -1,3 +1,3 @@
-<bitstream_annotations>
+<openfpga_bitstream_setting>
   <pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" source="eblif" content=".param LUT"/>
-</bitstream_annotations>
+</openfpga_bitstream_setting>