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update thru channel arch for avoid buggy pin locations

This commit is contained in:
tangxifan 2020-08-19 19:52:35 -06:00
parent 47f15729ad
commit 881672d46a
1 changed files with 8 additions and 1 deletions
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9
openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
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@ -188,7 +188,14 @@
<output name="d_out" num_pins="32"/>
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
<pinlocations pattern="perimeter"/>
<!--pinlocations pattern="custom">
<loc side="left"></loc>
<loc side="top">memory.clk</loc>
<loc side="right" yoffset="0">memory.waddr[0:4] memory.d_in[0:15] memory.wen</loc>
<loc side="right" yoffset="1">memory.raddr[0:4] memory.d_out[0:15]</loc>
<loc side="bottom">memory.waddr[5:9] memory.raddr[5:9] memory.d_in[16:31] memory.ren memory.d_out[16:31]</loc>
</pinlocations-->
</tile>
</tiles>
<!-- ODIN II specific config ends -->