From 881672d46a7ef58abf908fb9213340ca657162d7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 19:52:35 -0600
Subject: [PATCH] update thru channel arch for avoid buggy pin locations

---
 ...N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
index 7e4cf8e7a..ffefc9146 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
@@ -188,7 +188,14 @@
       <output name="d_out" num_pins="32"/>
       <clock name="clk" num_pins="1"/>
       <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="spread"/>
+      <pinlocations pattern="perimeter"/>
+      <!--pinlocations pattern="custom">
+        <loc side="left"></loc>
+        <loc side="top">memory.clk</loc>
+        <loc side="right" yoffset="0">memory.waddr[0:4] memory.d_in[0:15] memory.wen</loc>
+        <loc side="right" yoffset="1">memory.raddr[0:4] memory.d_out[0:15]</loc>
+        <loc side="bottom">memory.waddr[5:9] memory.raddr[5:9] memory.d_in[16:31] memory.ren memory.d_out[16:31]</loc>
+      </pinlocations-->
     </tile>
   </tiles>
   <!-- ODIN II specific config ends -->