clairexen
d3422f8a5e
Merge pull request #2211 from YosysHQ/mwk/fix-fmcombine-ff
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fmcombine: use the master ff cell type list
2020-07-02 17:43:48 +02:00
clairexen
5dbf91847a
Merge pull request #2210 from YosysHQ/mwk/fix-opt_merge
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opt_merge: use the master FF type list
2020-07-02 17:43:34 +02:00
Alberto Gonzalez
56f98b9e3d
qbfsat: Remove useless comment and #ifndef guards.
2020-07-01 19:55:16 +00:00
Alberto Gonzalez
3345d39e6f
qbfsat: Specify default values for some options in the help message.
2020-07-01 19:55:16 +00:00
Alberto Gonzalez
95e8016811
qbfsat: Clean up external executable command lines and update temporary directory name.
2020-07-01 19:55:16 +00:00
Alberto Gonzalez
8cd60be654
qbfsat: Clean up and refactor data structures into `qbfsat.h`.
2020-07-01 19:55:16 +00:00
Alberto Gonzalez
bbfa2d65fa
glift: Use ID() rather than string literals.
2020-07-01 19:51:48 +00:00
Alberto Gonzalez
eda1af73c4
glift: Use worker pattern.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
3eb2593876
glift: Add support for $_NAND_ and $_NOR_ cells.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
8cb1a86c23
glift: Add support for $_MUX_ and $_NMUX_ cells.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
23defc6fe9
glift: Add support for $_XOR_ and $_XNOR_ cells.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
209a123b97
glift: Add initial hierarchy support.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
20ad371724
glift: Replace `YS_OVERRIDE` with `override`.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
91c20fca72
glift: Add `-simple-cost-model` option
...
Rather than assigning specific weights to specific versions of taint tracking logic and summing the weights of all GLIFT cells, sum the following values for each GLIFT cell:
- 0 if the associated hole/$anyconst cell value is non-zero, i.e. reduced-precision taint tracking logic is chosen at this cell
- 1 if the associated hole/$anyconst cell value is zero, i.e. the full-precision taint tracking logic is chosen at this cell
This simplified cost modeling reduces the potential for the QBF-SAT solver to minimize taint tracking logic area but significantly simplifies the QBF-SAT problem.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
26bd686259
glift: Add `-instrument-more` option to add 4 more versions of taint tracking logic. Also refactor a bit and update help text.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
bc207d5426
glift: Change command names to better represent their functions.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
ddfb9f08e2
glift: Add `-create-imprecise` command, rename other commands, and re-work the help text.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
72cebef279
glift: Add replacement scoring and area minimization option.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
c36440a7ee
glift: Remove outputs by default; add `-keep-outputs` option; properly reset internal state between calls.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
19dafcd4f1
glift: Initial implementation of the `-sketchify` option.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
09848b3b9f
glift: Initial implementation of GLIFT model construction.
2020-07-01 19:51:45 +00:00
Alberto Gonzalez
5f45fe51ea
glift: Add skeleton for `glift` command.
2020-07-01 19:51:45 +00:00
clairexen
b1707407a0
Merge pull request #2138 from boqwxp/qbfsat-oflag
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qbfsat: Add `-O[012]` options to control pre-solving simplification with ABC
2020-07-01 16:35:27 +02:00
clairexen
2b0f6e24e2
Merge pull request #2206 from boqwxp/qbfsat-fix-name-specialization
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qbfsat: Fix name-based hole specialization
2020-07-01 16:34:32 +02:00
Marcelina Kościelnicka
e3564b4502
Add dfflegalize pass.
2020-07-01 01:57:15 +02:00
Marcelina Kościelnicka
7c91f13f51
fmcombine: use the master ff cell type list
2020-06-30 21:07:17 +02:00
Marcelina Kościelnicka
77b15dd8e9
opt_merge: use the master FF type list
2020-06-30 20:57:35 +02:00
clairexen
3fb5b4fd8a
Merge pull request #2199 from YosysHQ/mmicko/sim_memory
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sim - error when memrd and memwr detected
2020-06-30 17:12:51 +02:00
clairexen
275cee71f6
Merge pull request #2201 from YosysHQ/fix_test_cell_ilang
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Use ID macro to fix assertion
2020-06-30 17:11:13 +02:00
Alberto Gonzalez
83c595aaac
qbfsat: Add `-O[012]` options to control pre-solving simplification with ABC.
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Thanks to @mwk for the gate mapping part of the ABC scripts.
Co-Authored-By: Marcelina Kościelnicka <mwk@0x04.net>
2020-06-30 06:44:17 +00:00
Alberto Gonzalez
f544a2cc84
qbfsat: Fix name-based hole specialization.
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Look for unique connections in the containing module with the $anyconst port Y SigBit on the RHS and use those. If no such connection is found, fall back to using the name of the $anyconst port Y SigBit.
2020-06-30 01:53:21 +00:00
whitequark
a97c13f0ca
techmap: don't drop attributes on replaced cells.
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This was introduced in 76c4ee4ea5
.
Fixes #2204 .
2020-06-29 23:14:13 +00:00
Miodrag Milanović
4160acc0b1
Merge pull request #2200 from YosysHQ/mmicko/fix_expose
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expose pass fix
2020-06-29 15:16:29 +02:00
Miodrag Milanovic
405b4e97a1
Give error that options are exclusive
2020-06-29 14:45:49 +02:00
Miodrag Milanovic
0545a042f3
cleanup
2020-06-29 14:42:48 +02:00
Miodrag Milanovic
5aae936044
Use ID macro to fix assertion
2020-06-29 13:18:13 +02:00
Miodrag Milanovic
87717d67d1
expose pass fix
2020-06-29 11:56:43 +02:00
Miodrag Milanovic
48b6d3272c
sim - error when memrd and memwr detected
2020-06-29 10:33:39 +02:00
Xiretza
e2cfe57edd
test_cell: don't generate directional shifts with \B_SIGNED=1
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This was made an explicit error in e97e33d
, "kernel: require \B_SIGNED=0
on $shl, $sshl, $shr, $sshr.".
2020-06-28 21:30:16 +02:00
clairexen
c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs
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Use (and ignore) the expression provided to log_assert in NDEBUG builds
2020-06-25 18:21:51 +02:00
clairexen
21209d632e
Merge pull request #2135 from boqwxp/qbfsat-timeinfo
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log and qbfsat: Also include child process usage in `PerformanceTimer::query()` and report the time for each call to the QBF-SAT solver
2020-06-25 18:18:09 +02:00
clairexen
fb6441731a
Merge pull request #2093 from boqwxp/qbfsat-bugfixes
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qbfsat: Multiple bugfixes
2020-06-25 18:14:17 +02:00
Marcelina Kościelnicka
8f12c5b063
simplemap: Fix $dffsre mapping.
2020-06-23 23:16:43 +02:00
Marcelina Kościelnicka
88e7f90663
Update dff2dffe, dff2dffs, zinit to new FF types.
2020-06-23 18:24:53 +02:00
Marcelina Kościelnicka
832acc8648
Add new FF types to simplemap.
2020-06-23 15:40:02 +02:00
Marcelina Kościelnicka
119f79d8b9
Add support for new FF types in some opt passes.
2020-06-23 15:40:02 +02:00
Marcelina Kościelnicka
b0bee396a8
Add new builtin FF types
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The new types include:
- FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`)
- FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`)
- FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`)
- FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`)
- FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`)
- latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`)
The new FF types are not actually used anywhere yet (this is left
for future commits).
2020-06-23 15:40:02 +02:00
Alberto Gonzalez
a564cc806f
log, qbfsat: Include child process time in `PerformanceTimer::query()` and report the time for each call to the QBF-SAT solver.
2020-06-21 02:16:52 +00:00
Alberto Gonzalez
62a9e62a1b
qbfsat: Simplify solution recovery parsing and tweak the solution regexes.
2020-06-21 02:16:11 +00:00
Alberto Gonzalez
e1fedf054e
qbfsat: Avoid instantiating `AttrObject`s directly.
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Co-Authored-By: Claire Wolf <claire@symbioticeda.com>
2020-06-21 02:16:11 +00:00
Alberto Gonzalez
08cede4669
qbfsat: Simplify solution format and replace `SigBit::str()` with `log_signal()`.
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Co-Authored-By: Claire Wolf <claire@symbioticeda.com>
2020-06-21 02:16:11 +00:00
Alberto Gonzalez
4ab41c6435
qbfsat: Fixes three bugs.
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1. Infinite loop in the optimization procedure when the first solution found while maximizing is at zero.
2. A signed-ness issue when maximizing.
3. Erroneously entering bisection mode with no wire to optimize.
2020-06-21 02:16:11 +00:00
Alberto Gonzalez
a3d1f8637a
qbfsat: Use bit precise mapping for hole value wires and a more robust hole spec for writing to and specializing from a solution file.
2020-06-21 02:16:11 +00:00
whitequark
c8c3c7af87
Use [[maybe_unused]] instead of YS_ATTRIBUTE(unused).
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[[maybe_unused]] is available since C++17, so this commit adds
a polyfill YS_MAYBE_UNUSED. Once we require C++17 we can drop it.
2020-06-19 15:48:58 +00:00
whitequark
118e4caa37
Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().
2020-06-19 15:48:58 +00:00
whitequark
ede4b10da8
Merge pull request #2173 from whitequark/use-cxx11-final-override
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Use C++11 final/override/[[noreturn]]
2020-06-19 06:15:33 +00:00
whitequark
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
Alberto Gonzalez
76dfa81790
cutpoint: Improve efficiency by iterating over module ports instead of module wires.
2020-06-18 17:42:36 +00:00
N. Engelhardt
dfde1cf1c5
Merge pull request #2153 from boqwxp/splitnets-cleanup
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splitnets: Cleanup and efficiency improvements
2020-06-18 19:16:55 +02:00
whitequark
5439faebf9
Merge pull request #2142 from whitequark/splitnets-hdlname
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splitnets: propagate (*hdlname*) and disambiguate via start_offset
2020-06-18 16:57:24 +00:00
Anonymous Maarten
60fb9cabcf
msvc does not support designated initializers in structs
2020-06-17 16:20:52 +02:00
Alberto Gonzalez
f5d7cd60f5
splitnets: Clean up pseudo-private member usage
2020-06-13 05:47:55 +00:00
Alberto Gonzalez
b70de98bd1
splitnets: Slightly improve efficiency by avoiding some unnecessary lookups
2020-06-13 05:26:30 +00:00
whitequark
2139a5c21a
splitnets: propagate (*hdlname*) and disambiguate via start_offset.
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This allows reliably coalescing the split wires later.
2020-06-10 19:59:08 +00:00
Claire Wolf
0bd70e8222
Drive-by modernization in sat.cc
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-09 22:48:26 +02:00
Claire Wolf
3c7122c378
Do not optimize away FFs in "prep" and Verific fron-end
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-09 15:54:14 +02:00
whitequark
98e1080345
flatten: accept processes.
2020-06-09 09:56:23 +00:00
whitequark
fbb346ea91
flatten: preserve original object names via hdlname attribute.
2020-06-08 20:19:41 +00:00
whitequark
8d821dbbdb
flatten: only prepend $flatten once per wire.
2020-06-08 20:19:41 +00:00
whitequark
a1814b732f
flatten: make hygienic.
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Before this commit, `flatten` matched the template objects with
the newly created objects solely by their name. Because of this,
it could be confused by code such as:
module bar();
$dff a();
endmodule
module foo();
bar b();
$dff \b.a ();
endmodule
After this commit, `flatten` avoids every possible case of name
collision.
Fixes #2106 .
2020-06-08 19:30:21 +00:00
clairexen
369dcb4e82
Merge pull request #2085 from rswarbrick/select
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Silence warning in select.cc and pass some more args by ref
2020-06-08 15:55:52 +02:00
clairexen
0f209378a8
Merge pull request #2089 from rswarbrick/modports
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Simplify a modport check in hierarchy.cc
2020-06-08 15:48:11 +02:00
clairexen
fbd0d8d5f0
Merge pull request #2105 from whitequark/split-flatten-off-techmap
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Split `flatten` from `techmap` and simplify it
2020-06-08 15:27:15 +02:00
Marcelina Kościelnicka
28b9f49c94
fsm_extract: avoid calling log_signal to determine wire name
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log_signal can result in a string with spaces (when bit selection is
involved), which breaks the rule of IdString not containing whitespace.
Instead, remove the sigspec from the name entirely — given that the
resulting wire will have no users, it will be removed later anyway,
so its name doesn't really matter.
Fixes #2118
2020-06-08 03:49:58 +02:00
Eddie Hung
69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
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abc9: -dff improvements
2020-06-04 08:15:25 -07:00
whitequark
5a5a9b4ffe
flatten: clean up log messages.
2020-06-04 12:22:59 +00:00
whitequark
d731fe054b
flatten: topologically sort modules.
2020-06-04 12:22:59 +00:00
Eddie Hung
45cd323055
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes
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abc9: fixes around handling combinatorial loops
2020-06-03 17:35:46 -07:00
whitequark
6268bdfe6f
flatten: simplify.
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`flatten` cannot derive modules in most cases because that would just
yield processes, and it does not support `-autoproc`; in practice
`flatten` has to be preceded by a call to `hierarchy`, which makes
deriving unnecessary.
2020-06-04 00:02:12 +00:00
whitequark
d3e2100306
flatten: simplify. NFC.
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Remove redundant sigmaps.
2020-06-04 00:02:12 +00:00
whitequark
66255dab4e
flatten: simplify.
...
Flattening does not benefit from topologically sorting cells within
a module when processing them.
2020-06-04 00:02:12 +00:00
whitequark
5d2b6d1394
flatten: simplify. NFC.
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Flatten is non-recursive and doesn't need to keep track of handled
cells.
2020-06-04 00:02:12 +00:00
whitequark
3c3fa774e5
flatten: simplify. NFC.
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Flattening always does "non-recursive" mapping.
2020-06-04 00:02:12 +00:00
whitequark
e561a3a76f
flatten: simplify. NFC.
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The `celltypeMap` always maps `x` to `{x}`.
2020-06-04 00:02:12 +00:00
whitequark
6783876807
flatten: simplify. NFC.
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The `design` and `map` designs are always the same when flattening.
2020-06-04 00:02:12 +00:00
whitequark
9338ff66b9
RTLIL: factor out RTLIL::Module::addMemory. NFC.
2020-06-04 00:02:12 +00:00
whitequark
ebbbe2156e
flatten: rename techmap-related stuff. NFC.
2020-06-04 00:02:12 +00:00
whitequark
76c4ee4ea5
techmap, flatten: remove dead options.
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After splitting the passes, some options can never be activated,
and most conditions involving them become dead. Remove them, and also
all of the newly dead code.
2020-06-04 00:02:12 +00:00
whitequark
6ac54a74fe
flatten: split from techmap.
...
Although the two passes started out very similar, they diverged over
time and now have little in common. Moreover, `techmap` is extremely
complex while `flatten` does not have to be, and this complexity
interferes with improving `flatten`.
2020-06-03 15:34:03 +00:00
whitequark
fb5b070e7e
techmap: remove dead variable. NFC.
2020-06-03 01:44:06 +00:00
whitequark
0a74368bfc
techmap: use C++11 default member initializers. NFC.
2020-06-02 23:43:20 +00:00
whitequark
f3e86bb32a
techmap: simplify.
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`rewrite_filename` is already called in `Frontend::extra_args`.
2020-06-02 23:43:20 +00:00
whitequark
68d747f767
techmap: use +/techmap.v instead of an ad-hoc code generator.
2020-06-02 23:43:20 +00:00
clairexen
ff785cdb46
Merge pull request #1862 from boqwxp/cleanup_techmap
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Clean up `passes/techmap/techmap.cc`
2020-05-31 20:40:48 +02:00
Eddie Hung
08d9703ecb
abc9_ops: fix comment
2020-05-30 09:01:03 -07:00
Eddie Hung
fe273faad1
Merge pull request #2081 from YosysHQ/eddie/blackbox_ast
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blackbox: use Module::makeblackbox() method
2020-05-30 08:59:20 -07:00
Eddie Hung
ea4374a223
abc9_ops: update messaging (credit to @Xiretza for spotting)
2020-05-30 08:57:48 -07:00
clairexen
ea46ed81f9
Merge pull request #2018 from boqwxp/qbfsat-timeout
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smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
2020-05-30 15:04:51 +02:00
Eddie Hung
b17e8495b8
abc9_ops: optimise to not derive unless attribute exists
2020-05-29 17:33:10 -07:00
Eddie Hung
d3b53bc495
abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_
2020-05-29 17:17:40 -07:00
clairexen
94c1035389
Merge pull request #1885 from Xiretza/mod-rem-cells
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Fix modulo/remainder semantics
2020-05-29 16:37:23 +02:00
clairexen
5874a14d65
Merge pull request #2017 from boqwxp/qbfsat-cvc4
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qbfsat: Add support for CVC4.
2020-05-29 16:23:10 +02:00
clairexen
1c8d5a08a0
Merge pull request #2016 from boqwxp/qbfsat-yices
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qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
2020-05-29 16:21:45 +02:00
Xiretza
edd8ff2c07
Add flooring division operator
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The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.
This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
2020-05-28 22:59:04 +02:00
Xiretza
17163cf43a
Add flooring modulo operator
...
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).
This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
2020-05-28 22:59:03 +02:00
whitequark
0d99522b3c
Merge pull request #2095 from rswarbrick/hier-typo
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Fix small typos in documentation for hierarchy command
2020-05-28 10:49:14 +00:00
Rupert Swarbrick
1158bbf7db
Fix small typos in documentation for hierarchy command
2020-05-28 11:39:44 +01:00
Alberto Gonzalez
5896ffd56f
printattrs: Simplify `get_indent_str()`.
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Co-Authored-By: Xiretza <xiretza@xiretza.xyz>
2020-05-28 05:34:28 +00:00
Alberto Gonzalez
f671c99cb8
printattrs: Refactor indentation string building for clarity.
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Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-05-27 23:15:07 +00:00
Rupert Swarbrick
d681c9df85
Pass some more args by reference in select.cc
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Before this patch, the code passed around std::string objects by
value. It's probably not a hot-spot, but it can't hurt to avoid the
copying.
Removing the copy and clean-up code means the resulting code is ~6.1kb
smaller when compiled with GCC 9.3 and standard settings.
2020-05-27 09:42:23 +01:00
Rupert Swarbrick
061d1f0c07
Minor optimisations in select.cc's match_ids function
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- Pass a string argument by reference
- Avoid multiple calls to IdString::str and IdString::c_str
- Avoid combining checks for size > 0 and first char (C strings are
null terminated, so foo[0] != '\0' implies that foo has positive
length)
2020-05-27 09:36:33 +01:00
Rupert Swarbrick
0d9beb5b2e
Silence warning in select.cc
...
With GCC 9.3, at least, compiling select.cc spits out a warning about
an implausible bound being passed to strncmp. This comes from inlining
IdString::compare(): it turns out that passing std::string::npos as a
bound to strncmp triggers it.
This patch replaces the compare call with a memcmp with the same
effect. The repeated calls to IdString::c_str are slightly
inefficient, but I'll address that in a follow-up commit.
2020-05-27 09:34:15 +01:00
Alberto Gonzalez
e50e4ee285
printattrs: Use `flags` to pretty-print the `RTLIL::Const` appropriately.
...
Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-05-27 08:00:00 +00:00
Alberto Gonzalez
b8365547e9
misc: Add `printattrs` command.
2020-05-27 08:00:00 +00:00
Rupert Swarbrick
7746bba69a
Simplify a modport check in hierarchy.cc
...
This code originally comes from commit 458a940
. When an interface is
used via a modport, code in genrtlil.cc sets '\\interface_type' and
'\\interface_modport' properties on the wire.
In hierarchy.cc, we pick up the modport name and add it to a dict
called modports_used_in_submodule (that maps connection source to
modport name).
Before this patch, the modport name is retrieved as a strpool and then
iterated over in an arbitrary order, discarding all entries but the
last. In practice, the pool will always have 0 or 1 entries because
the string used to construct it is a valid identifier, so doesn't
contain any pipe symbols.
This patch changes the code to retrieve the modport name as just a
string. This will have the same effect in practice, but may be a bit
less confusing!
The code also gets moved down closer to where the result is used,
which might be a bit more efficient since we won't always get as far
as the check.
The patch also removes some commented-out code, which I think was
intended to add some typechecking at some point, but was never
implemented. Since this dates back to October 2018, I think it makes
more sense to just take it out.
2020-05-26 16:50:42 +01:00
Eddie Hung
00c5ceb1f2
abc9_ops: -prep_xaiger exclude (* abc9_keep *) wires from toposort
2020-05-25 16:40:53 -07:00
Alberto Gonzalez
9847a4eea8
smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
2020-05-25 20:39:30 +00:00
Alberto Gonzalez
f9eef5e3f7
qbfsat: Add support for CVC4.
2020-05-25 20:39:03 +00:00
Alberto Gonzalez
903456c267
qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
...
Ensures that "BV" is the logic whenever solving an exists-forall problem with Yices, moves the "(set-logic ...)" directive above any non-info line, sets the `ef-max-iters` parameter to a very high number when using Yices in exists-forall mode so as not to prematurely abandon difficult problems, and does not provide the incompatible "--incremental" Yices argument when in exists-forall mode.
2020-05-25 20:38:29 +00:00
Eddie Hung
721283ac2a
blackbox: re-use existing Module::makeblackbox() method
2020-05-25 10:53:49 -07:00
Eddie Hung
7bad23f19c
abc9_ops: -reintegrate to preserve flop names
2020-05-25 08:43:33 -07:00
clairexen
ae11156c90
Merge pull request #2015 from boqwxp/qbfsat-bisection
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qbfsat: Add an iterative bisection optimization method and make it the default.
2020-05-25 15:50:18 +02:00
Alberto Gonzalez
ac41f8a9c7
qbfsat: Remove cruft inadvertently left untouched in commit 86fc49a9d6
.
2020-05-23 00:53:09 +00:00
Alberto Gonzalez
aea0fd5ed4
qbfsat: Add bisection mode and make it the default.
...
Also adds `-nooptimize` and reorganizes `qbfsat.cc` a bit.
2020-05-23 00:53:09 +00:00
Eddie Hung
4f0f321169
abc9_ops: update comment
2020-05-21 21:39:13 -07:00
Miodrag Milanović
637650597b
Merge pull request #2059 from boqwxp/logger-vector-to-dict
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log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.
2020-05-21 15:36:30 +02:00
Eddie Hung
2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
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abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
2020-05-18 08:06:50 -07:00
Alberto Gonzalez
8297afe925
log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.
2020-05-15 00:55:32 +00:00
Eddie Hung
67fc0c3698
abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
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instead of moving them to $__ prefix
2020-05-14 16:44:35 -07:00
Eddie Hung
07eecff9cc
Merge pull request #2055 from YosysHQ/eddie/logger_multiple
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logger: fix for multiple calls with same pattern
2020-05-14 15:30:08 -07:00
Alberto Gonzalez
e173291649
techmap: Replace naughty `const_cast<>()`s.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:55 +00:00
Alberto Gonzalez
97fd304cbe
techmap: Replace pseudo-private member usage with the range accessor function and some naughty `const_cast<>()`s.
2020-05-14 20:06:55 +00:00
Eddie Hung
36bb201dd9
techmap: sort celltypeMap as it determines techmap order
2020-05-14 20:06:55 +00:00
Alberto Gonzalez
ce62d0751a
Replace `std::set`s using custom comparators with `pool`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:55 +00:00
Eddie Hung
dabeb1e8a1
techmap: prefix special wires with backslash for use as IdString
2020-05-14 20:06:55 +00:00
Alberto Gonzalez
bd54d67ad4
Further clean up `passes/techmap/techmap.cc`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
982562ff13
Use `emplace()` for more efficient insertion into various `dict`s.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
c658d9d59d
Build constant bits directly rather than constructing an object and copying its bits.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
f235f212ea
Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
6294621825
Use `emplace()` rather than `insert()`.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
dfcb936cd5
Clean up pseudo-private member usage and ensure range iteration uses references where possible to avoid unnecessary copies.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
a4755c50c3
Clean up extraneous buffer.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
7857782575
Replace `std::map` with `dict` for `unique_bit_id`.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
6d64d768b0
Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and `cellbits_to_tplbits`.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
5cb4ae4666
Replace `std::map` with `dict` for `connbits_map`, `cell_to_inbit`, and `outbit_to_cell`.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
c43017fc08
Replace `std::map` with `dict` for `TechmapWires` type.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
644e55b3d3
Replace `std::map` with `dict` for `celltypeMap`.
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
67f4046c05
Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`.
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
64c16f8c13
Replace `std::map` with `dict` for `positional_ports`.
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
2fb4931e5b
Add specialized `hash()` for type `dict` and use a `dict` instead of a `std::map` for `techmap_cache` and `techmap_do_cache`.
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
437f3fb342
Replace `std::map` with `dict` for `simplemap_mappers`.
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
99b586b283
Use `nullptr` instead of `NULL` in `passes/techmap/techmap.cc`.
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
5f7f213c7f
Replace `std::string` and `RTLIL::IdString` with `IdString` in `passes/techmap/techmap.cc`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
e49fdee404
Do not modify design modules while iterating over `modules()`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
985a29ff3b
Clean up pseudo-private member usage, superfluous `std::vector` instantiation, and `RTLIL::id2cstr()` usage in `passes/techmap/techmap.cc`.
2020-05-14 20:06:53 +00:00
Eddie Hung
7b3a4a1fff
opt_expr: Sx to Sz; spotted by @Xiretza
2020-05-14 12:14:23 -07:00
Eddie Hung
73b7ea713c
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758
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opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
2020-05-14 11:56:22 -07:00
Eddie Hung
425867d175
logger: clean up doc
2020-05-14 10:38:31 -07:00
Eddie Hung
02df0198b6
abc9_ops: -prep_hier to create unmap module that removes Q's (* init *)
2020-05-14 10:33:57 -07:00
Eddie Hung
13f9d65b6f
abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it
2020-05-14 10:33:57 -07:00
Eddie Hung
fa31e84112
Fix broken test when ignoring abc9_flop with init == 1'b1
2020-05-14 10:33:57 -07:00
Eddie Hung
97a0a04314
abc9_ops/xaiger: further reducing Module::derive() calls by ...
...
replacing _all_ (* abc9_box *) instantiations with their derived types
2020-05-14 10:33:57 -07:00
Eddie Hung
e79127fceb
Cleanup; reduce Module::derive() calls
2020-05-14 10:33:57 -07:00
Eddie Hung
8d34aee3d5
abc9: update to =_$abc9_flops pattern which includes whiteboxes
2020-05-14 10:33:57 -07:00
Eddie Hung
f652a9c11c
abc9_ops: update docs
2020-05-14 10:33:57 -07:00
Eddie Hung
57c478c537
abc9: only do +/abc9_map if `DFF
2020-05-14 10:33:57 -07:00
Eddie Hung
2946bb60e9
abc9: rework submod -- since it won't move (* keep *) cells
2020-05-14 10:33:56 -07:00
Eddie Hung
b65610fb62
abc9_ops: move assert
2020-05-14 10:33:56 -07:00
Eddie Hung
ed7cb0b095
abc9: put 'aigmap' back
2020-05-14 10:33:56 -07:00
Eddie Hung
b3e2538a14
abc9_ops: fix bypass boxes using (* abc9_bypass *)
2020-05-14 10:33:56 -07:00
Eddie Hung
d5a8aaba8c
abc9_ops: tidy up, suppress error if no boxes/holes
2020-05-14 10:33:56 -07:00
Eddie Hung
e2044fd9c7
abc9_ops: -prep_delays to not insert delay box if input connection is const
2020-05-14 10:33:56 -07:00
Eddie Hung
8b5fb99245
abc9_ops: cleanup; -prep_dff -> -prep_dff_submod
2020-05-14 10:33:56 -07:00
Eddie Hung
7cd3f4a79b
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
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Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
2020-05-14 10:33:56 -07:00
Eddie Hung
bb840cca9c
abc9_ops: -reintegrate to handle $_FF_; cleanup
2020-05-14 10:33:56 -07:00
Eddie Hung
c50601e35e
abc9: restore selected_modules()
2020-05-14 10:33:56 -07:00
Eddie Hung
48052ad813
abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
2020-05-14 10:33:56 -07:00
Eddie Hung
4cec21b93e
abc9_ops: -prep_dff_map to error if async flop found
2020-05-14 10:33:56 -07:00
Eddie Hung
c41c180f68
abc9: remove redundant wbflip
2020-05-14 10:33:56 -07:00
Eddie Hung
ec4bbb1444
abc9: generate $abc9_holes design instead of <name>$holes
2020-05-14 10:33:56 -07:00
Eddie Hung
c52bb11fb6
abc9_ops: more robust
2020-05-14 10:33:56 -07:00
Eddie Hung
8d7b3c06b2
abc9: suppress warnings when no compatible + used flop boxes formed
2020-05-14 10:33:56 -07:00
Eddie Hung
fb447951be
abc9: cleanup
2020-05-14 10:33:56 -07:00
Eddie Hung
8bad885e78
abc9_ops: -prep_dff_map to check $_DFF_[NP]_.Q drives module output
2020-05-14 10:33:56 -07:00
Eddie Hung
489e83fc1e
abc9_ops: do away with '$abc9_cells' selection
2020-05-14 10:33:56 -07:00
Eddie Hung
043ad8e76c
abc9_ops: use new 'design -delete' and 'select -unset'
2020-05-14 10:33:56 -07:00
Eddie Hung
509de98468
submod: revert accidental change
2020-05-14 10:33:56 -07:00
Eddie Hung
e38b1280f9
abc9_ops: -prep_dff_map to warn if no specify cells
2020-05-14 10:33:56 -07:00
Eddie Hung
a1ae5845f8
abc9_ops: -prep_dff_map to cope with plain $_DFF_[NP]_ flops
2020-05-14 10:33:56 -07:00
Eddie Hung
6b3aa91a2a
abc9: cleanup
2020-05-14 10:33:56 -07:00
Eddie Hung
edacb8f437
abc9_ops: do not use (* abc9_init *)
2020-05-14 10:33:56 -07:00
Eddie Hung
95763c8d18
abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes
2020-05-14 10:33:56 -07:00
Eddie Hung
accfc70fc2
abc9: fix behaviour and help for -box option
2020-05-14 10:33:56 -07:00
Eddie Hung
65395168a0
logger: fix for multiple calls with same pattern
2020-05-14 10:32:07 -07:00
Eddie Hung
cd92a706ae
Fix whitespace
2020-05-14 09:51:17 -07:00
Eddie Hung
5be4b00a0d
opt_clean: improve warning message
2020-05-14 00:59:38 -07:00
Eddie Hung
fc9fb09a91
opt_clean: rminit without -purge; also remove if consistent with const..
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warn otherwise
2020-05-14 00:31:08 -07:00
Eddie Hung
68b31f5e99
opt_clean: really make 'clean' identical to 'opt_clean' by rminit too
2020-05-14 00:31:08 -07:00
Eddie Hung
9694dc42dd
opt_expr: consume_x to require/imply !keepdc
2020-05-08 11:12:43 -07:00
Eddie Hung
17f4e06247
opt_expr: restore consume_x; use for coarse grained too
2020-05-08 11:07:44 -07:00
Claire Wolf
0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990
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Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
2020-05-07 18:11:48 +02:00
Claire Wolf
5c82c19b4b
Merge pull request #2014 from YosysHQ/claire/fixoptalu
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Fix the other "opt_expr -fine" bug introduced in 213a89558
2020-05-03 11:56:29 +02:00
Claire Wolf
2285cf1219
Fix the other "opt_expr -fine" bug introduced in 213a89558
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 21:50:43 +02:00
Claire Wolf
885deb4e88
Fix the other "opt_expr -fine" bug introduced in 213a89558
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 21:34:24 +02:00
Eddie Hung
da7da44919
abc9_ops: -reintegrate to be sensitive to start_offset too
2020-05-02 11:19:04 -07:00
Claire Wolf
c3e5a070ea
Add plusargs for output files in test_autotb output
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Claire Wolf
ca3fc3c882
Merge pull request #2010 from YosysHQ/claire/fixopt
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Fix "opt_expr -fine" bug introduced in 213a89558
2020-05-02 11:20:02 +02:00
Claire Wolf
8ee32adac3
Fix "opt_expr -fine" bug introduced in 213a89558
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-01 20:12:16 +02:00
whitequark
b43c282e4e
Add WASI platform support.
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This includes the following significant changes:
* Patching ezsat and minisat to disable resource limiting code
on WASM/WASI, since the POSIX functions they use are unavailable.
* Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
does not support spawning subprocesses (i.e. Emscripten or WASI).
This definition hides the definition of `run_command()`.
* Adding a new Makefile flag, DISABLE_SPAWN, present in the same
condition. This flag disables all passes that require spawning
subprocesses for their function.
2020-04-30 18:56:25 +00:00
Eddie Hung
b5f38f8342
opt_expr: const_xnor replacement to pad Y with 1'b1
2020-04-24 14:13:45 -07:00
Eddie Hung
56dd036b97
bugpoint: improve messaging
2020-04-24 13:41:19 -07:00
Eddie Hung
e602184856
bugpoint: (* keep *) to (* bugpoint_keep *); also apply to modules/cells
2020-04-24 13:26:04 -07:00
Eddie Hung
4bfe6ebea9
bugpoint: skip ports with (* keep *) on; add header
2020-04-24 11:17:09 -07:00
Eddie Hung
83570bc0da
opt_expr: more fixes for $xor/$xnor
2020-04-24 11:15:29 -07:00
Eddie Hung
90b71eb84b
opt_expr: do not group by X, more fixes
2020-04-23 18:15:07 -07:00
Eddie Hung
e7058593f4
opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
2020-04-23 15:57:48 -07:00
Eddie Hung
bf021a0e1f
bugpoint: improve help text
2020-04-23 12:16:55 -07:00
Eddie Hung
b048afc3a6
Merge pull request #1974 from YosysHQ/eddie/abc9_disable_mfs
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abc9: tolerate &mfs failure by writing output file before calling it (and using that if it fails)
2020-04-23 06:43:30 -07:00
Claire Wolf
dc9a72bc8d
Merge pull request #1989 from boqwxp/qbfsat_anyconst_sourcelocs
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qbfsat: Make hole name recovery from source locations more robust.
2020-04-23 11:34:19 +02:00
Claire Wolf
1797c574da
Merge pull request #1988 from boqwxp/qbfsat
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qbfsat: Add `-assume-negative-polarity` option.
2020-04-23 11:33:54 +02:00
Alberto Gonzalez
4ee8452d34
qbfsat: Make hole name recovery more robust. Allow multiple cell types to share the same source location as long as only one `$anyconst` or `$anyseq` has that location.
2020-04-23 05:45:44 +00:00
Alberto Gonzalez
7369e6b26b
qbfsat: Add `-assume-negative-polarity` option.
2020-04-23 04:06:15 +00:00
Eddie Hung
592baebd22
xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only
2020-04-22 17:43:25 -07:00
Eddie Hung
fa9df06c9d
Merge pull request #1949 from YosysHQ/eddie/select_blackbox
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select: do not select inside black-/white- boxes unless '=' prefix used
2020-04-22 15:35:05 -07:00
Claire Wolf
beb9e4b299
Update passes/cmds/select.cc
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-04-22 21:31:32 +02:00
Eddie Hung
7f33a0294b
Cleanup use of hard-coded default parameters in light of #1945
2020-04-22 12:02:30 -07:00
Eddie Hung
eaa5a3e786
select: do not select black/white boxes by default, '=' prefix to do so
2020-04-22 10:15:56 -07:00
Eddie Hung
28623f19ee
Merge pull request #1950 from YosysHQ/eddie/design_import
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design: -import to not count black/white-boxes as candidates for top
2020-04-22 09:32:13 -07:00
Claire Wolf
c32b4bded5
Merge pull request #1976 from YosysHQ/dave/fix-sim-const
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sim: Fix handling of constant-connected cell inputs at startup
2020-04-22 16:57:34 +02:00
Marcelina Kościelnicka
cd82afb740
bugpoint: Don't remove modules or cells while iterating over them.
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Reported by @ZirconiumX.
2020-04-22 00:09:01 +02:00
Marcelina Kościelnicka
846c79b312
hierarchy: Convert positional parameters to named.
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Fixes #1821 .
2020-04-21 19:09:00 +02:00
Claire Wolf
d834cc7afb
Add '=' selection pattern prefix for non-blackbox only patterns
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-21 14:23:24 +02:00
David Shah
abf81c7639
sim: Fix handling of constant-connected cell inputs at startup
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-21 08:58:52 +01:00
Eddie Hung
3d7b983351
abc9: tolerate ABC nonzero exit code if output.aig; write before &mfs
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Re-enable mfs for xilinx/ecp5 speculatively -- if it fails, use pre-mfs
result
2020-04-20 11:26:11 -07:00
Eddie Hung
a998a4155d
xilinx/ecp5: disable abc9's "&mfs" optimisation
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Can sometimes fire an assertion, e.g. #1962
2020-04-20 10:30:10 -07:00
Eddie Hung
8c992ca47f
abc9: -prep_lut to be more robust
2020-04-20 09:39:35 -07:00
David Shah
586739ecf3
qbfsat: Fix illegal use of 'stdout' identifier
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-17 08:42:39 +01:00
whitequark
69743aad42
Merge pull request #1864 from boqwxp/cleanup_techmap_abc
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Clean up pseudo-private member usage and simplify `passes/techmap/abc.cc`
2020-04-17 02:25:18 +00:00
whitequark
f2064c8131
Merge pull request #1888 from boqwxp/cleanup_scatter
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Clean up `passes/cmds/scatter.cc`.
2020-04-17 02:21:23 +00:00
whitequark
5c428996a9
Merge pull request #1882 from boqwxp/cleanup_rename
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Clean up pseudo-private member usage in `passes/cmds/rename.cc`.
2020-04-17 02:20:54 +00:00
Eddie Hung
dac5adde12
design: -import to not count black/white-boxes as candidates for top
2020-04-16 12:46:07 -07:00
Eddie Hung
47c8ee7fe4
select: do not select inside blackboxes
2020-04-16 12:23:34 -07:00
Alberto Gonzalez
2e3647f567
Use `dict` instead of `std::map`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-04-16 18:56:50 +00:00
Alberto Gonzalez
b94f38295a
Revert to `stringf()` rather than stringstreams.
2020-04-16 18:56:50 +00:00
Alberto Gonzalez
6081c1bbd3
Clean up pseudo-private member usage in `passes/cmds/rename.cc`.
2020-04-16 18:56:50 +00:00
Alberto Gonzalez
ff8be2364e
Replace `std::map` with `dict`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-04-16 18:49:55 +00:00
Alberto Gonzalez
0424555702
Replace pseudo-private member access to `connections_` in `passes/cmds/scatter.cc`.
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Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
2020-04-16 18:49:55 +00:00
Alberto Gonzalez
0787af947f
Clean up `passes/cmds/scatter.cc`.
2020-04-16 18:49:55 +00:00
Eddie Hung
254d38ca67
select: add select -unset option
2020-04-16 10:51:58 -07:00
Eddie Hung
8d3f6d0d79
Merge pull request #1928 from YosysHQ/eddie/design_delete
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kernel: add design -delete option
2020-04-16 10:51:09 -07:00
Eddie Hung
aa552cefa3
Merge pull request #1927 from YosysHQ/eddie/design_remove_assert
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kernel: Design::remove(RTLIL::Module *) to check refcount_modules_
2020-04-16 08:06:12 -07:00
Eddie Hung
a9ec0defb9
kernel: add design -delete option
2020-04-16 08:05:18 -07:00
Marcelina Kościelnicka
2f8541a92e
opt_expr: Fix X and CO outputs for $alu identity-mapping rules.
2020-04-16 11:48:29 +02:00
Eddie Hung
33b0ac9269
Merge pull request #1933 from YosysHQ/eddie/zinit_more
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zinit: handle $__DFFS?E?_[NP][NP][01] too
2020-04-15 08:36:25 -07:00
N. Engelhardt
0b7a5879e5
Merge pull request #1830 from boqwxp/qbfsat
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Add `qbfsat` command to integrate exists-forall solving and specialization
2020-04-15 17:33:50 +02:00
David Shah
7ad8b24280
Merge pull request #1897 from YosysHQ/dave/bram-rejection-fix
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memory_bram: Fix ignorance of valid, matched rules
2020-04-15 16:10:38 +01:00
Marcelina Kościelnicka
38a0c30d65
Get rid of dffsr2dff.
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This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part. Thus, it never
actually does anything and can be safely removed.
2020-04-15 16:22:37 +02:00
Marcelina Kościelnicka
85166633bc
opt_clean: Add missing assignments to opt.did_something.
2020-04-15 16:20:56 +02:00
Marcelina Kościelnicka
d7da491002
setundef: Improve error messages.
...
Fixes #1092 .
2020-04-15 16:13:28 +02:00
Marcelina Kościelnicka
4c52691a58
abc9_ops: Add a check ensuring that connected port actually exists.
2020-04-15 08:11:15 +02:00
Eddie Hung
a8ab74285b
zinit: handle $__DFFS?E?_[NP][NP][01] too
2020-04-14 13:08:23 -07:00
Marcelina Kościelnicka
6c16fd760b
opt_expr: Add more $alu optimizations.
...
Detect the places in the $alu where the carry bit is constant (due to
const A[i] == B[i] ^ BI) and split it into smaller $alu at these points.
Also, make the existing const-carry detection for low bits more generic
(now handles cases where both BI and CI are constant, but not equal to
one another).
Fixes #1912 .
2020-04-14 21:48:13 +02:00
Marcelina Kościelnicka
7a36728b2f
dffinit: Avoid setting init parameter to zero-length value.
...
Fixes #1704 .
2020-04-14 19:52:19 +02:00
Eddie Hung
75bb2c8c24
design: do not delete when iterating over Design::modules() directly
2020-04-14 10:43:05 -07:00
Eddie Hung
3a27906ac6
abc9_exe: verify -> &verify -s
2020-04-14 08:21:26 -07:00
Eddie Hung
843201ec96
techmap: fix error message
2020-04-14 08:17:02 -07:00
Alberto Gonzalez
4ccaf048a5
Simplify `passes/techmap/abc.cc` and remove superfluous `RTLIL::SigSpec` constructions.
...
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-04-14 02:39:44 +00:00
Eddie Hung
b75c5bf743
zinit: resolve one more comment by @mwkmwkmwk
2020-04-13 15:25:37 -07:00
Eddie Hung
c6afce7638
zinit: fix review comments from @mwkmwkmwk
2020-04-13 15:16:51 -07:00
Eddie Hung
70bca35f9c
zinit: operate on $adff, erase (* init *) entries on consumption
2020-04-13 14:28:53 -07:00
Eddie Hung
1cdfdbc6d1
Fix S/R comment; thanks @mwkmwkmwk
2020-04-13 13:45:18 -07:00
Eddie Hung
4617aa8ccd
zinit to transform set/reset value of $_DFF_[NP][NP][01]_
2020-04-13 13:45:18 -07:00
Eddie Hung
b97a9cd3f3
Supress error for unhandled \init if whole module selected
2020-04-13 13:16:49 -07:00
Marcelina Kościelnicka
840bb17089
opt_expr: Optimize multiplications with low 0 bits in operands.
...
Fixes #1500 .
2020-04-13 16:52:22 +02:00
Alberto Gonzalez
e300766fb3
Use `pool` instead of `std::set`.
2020-04-11 09:41:09 +00:00
Alberto Gonzalez
73bd7fb01d
Use `dict` instead of `std::map`.
2020-04-11 06:53:59 +00:00
David Shah
85672a6c1f
memory_bram: Fix ignorance of valid, matched rules
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-10 21:48:04 +01:00
whitequark
93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style
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ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
2020-04-10 14:51:01 +00:00
Miodrag Milanovic
0d789c5a3b
Support custom PROGRAM_PREFIX
2020-04-10 10:38:40 +02:00
Marcelina Kościelnicka
516857f3ba
[NFCI] Deduplicate builtin FF cell types list
...
A few passes included the same list of FF cell types. Make it a global
const instead.
The zinit pass also seems to include a list like that, but given that
it seems to be completely broken at the time (see #1568 discussion),
I'm going to pretend I didn't see that.
2020-04-09 18:05:06 +02:00
N. Engelhardt
7f33d43e3b
Merge pull request #1890 from boqwxp/cleanup_memory_collect
...
Clean up `passes/memory/memory_collect.cc`.
2020-04-09 14:01:29 +02:00
N. Engelhardt
ed738b8ddb
Merge pull request #1889 from boqwxp/cleanup_memory_unpack
...
Clean up `passes/memory/memory_unpack.cc`.
2020-04-09 14:00:44 +02:00
Alberto Gonzalez
de5e6fa56a
Clean up `passes/sat/qbfsat.cc`.
...
Makes various cosmetic fixes, removes superfluous `hasPort()` check, and uses `emplace_back()` instead of `push_back()`.
2020-04-09 07:47:44 +00:00
Alberto Gonzalez
652050b273
Clean up `passes/memory/memory_collect.cc`.
2020-04-09 05:43:05 +00:00
Alberto Gonzalez
685dc37d27
Clean up `passes/memory/memory_unpack.cc`.
2020-04-09 05:38:36 +00:00
Alberto Gonzalez
83222193af
Clean up `passes/techmap/hilomap.cc`.
2020-04-09 05:28:32 +00:00
whitequark
42e7e44207
Merge pull request #1857 from whitequark/splitnets-skip-processes
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splitnets: skip modules with processes
2020-04-09 04:03:30 +00:00
Alberto Gonzalez
64a5936bd7
Clean up `passes/cmds/connect.cc`.
2020-04-08 22:11:06 +00:00
Alberto Gonzalez
194354e128
Remove `$anyconst` cells before specialization to eliminate warnings and the need to run `opt_clean`.
2020-04-07 03:29:54 +00:00
whitequark
b350398c04
Merge pull request #1874 from boqwxp/cleanup_show
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Clean up `passes/cmds/show.cc`.
2020-04-06 18:32:20 +00:00
whitequark
8ca12e0c42
Merge pull request #1861 from boqwxp/cleanup_hierarchy_submod
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Clean up `passes/hierarchy/submod.cc`.
2020-04-06 18:32:10 +00:00
Alberto Gonzalez
f4346a0400
Use more descriptive variable name.
...
Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-04-06 14:48:27 +00:00
Alberto Gonzalez
d6de14a0d6
Use more descriptive variable name.
...
Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-04-06 14:37:07 +00:00
whitequark
ebf23cd62e
Merge pull request #1870 from boqwxp/cleanup_setattr
...
Clean up `passes/cmds/setattr.cc`.
2020-04-06 11:04:49 +00:00
whitequark
df95dc7d4a
Merge pull request #1872 from boqwxp/cleanup_copy
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Clean up private member usage in `passes/cmds/copy.cc`.
2020-04-06 11:03:46 +00:00
whitequark
41f0c38478
Merge pull request #1871 from boqwxp/cleanup_splice
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Clean up `passes/cmds/splice.cc`.
2020-04-06 11:03:34 +00:00
whitequark
db66371915
Merge pull request #1869 from boqwxp/cleanup_connwrappers
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Clean up `passes/cmds/connwrappers.cc`.
2020-04-06 11:01:44 +00:00
whitequark
30934e425d
Merge pull request #1868 from boqwxp/cleanup_delete
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Clean up `passes/cmds/delete.cc`.
2020-04-06 10:58:38 +00:00
whitequark
d3615ee445
Merge pull request #1867 from boqwxp/cleanup_stat
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Clean up `passes/cmds/stat.cc`.
2020-04-06 10:58:02 +00:00
whitequark
75d39c6fdf
Merge pull request #1866 from boqwxp/cleanup_test_autotb
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Clean up `passes/tests/test_autotb.cc`.
2020-04-06 10:56:45 +00:00
whitequark
79c6149069
Merge pull request #1865 from boqwxp/cleanup_dfflibmap
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Clean up `passes/techmap/dfflibmap.cc`.
2020-04-06 10:56:22 +00:00
whitequark
8340660518
Merge pull request #1863 from boqwxp/cleanup_techmap_extract
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Clean up `passes/techmap/extract.cc`.
2020-04-06 10:55:50 +00:00
whitequark
0d69d532e0
Merge pull request #1859 from boqwxp/design_duplicate
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Add `-push-copy` option to the `design` command.
2020-04-06 10:39:26 +00:00
Alberto Gonzalez
57f48f94c2
Clean up `passes/cmds/show.cc`.
2020-04-06 08:51:25 +00:00
Alberto Gonzalez
fdeeb48e62
Clean up private member usage in `passes/cmds/bugpoint.cc`.
2020-04-06 08:35:09 +00:00
Alberto Gonzalez
2dd09ab611
Clean up private member usage in `passes/cmds/copy.cc`.
2020-04-06 08:26:10 +00:00
Alberto Gonzalez
5e9c88501e
Clean up `passes/cmds/splice.cc`.
2020-04-06 07:42:46 +00:00
Alberto Gonzalez
2e27ddd511
Clean up `passes/cmds/setattr.cc`.
2020-04-06 06:52:18 +00:00
Alberto Gonzalez
968230261f
Clean up `passes/cmds/connwrappers.cc`.
2020-04-06 06:11:25 +00:00
Alberto Gonzalez
1226d41c61
Clean up `passes/cmds/delete.cc`.
2020-04-06 05:09:43 +00:00
Alberto Gonzalez
b39a0d77ab
Clean up `passes/cmds/stat.cc`.
2020-04-06 04:39:18 +00:00
Alberto Gonzalez
438d2e0025
Clean up `passes/tests/test_autotb.cc`.
2020-04-06 04:25:21 +00:00
Alberto Gonzalez
f3e282a97c
Clean up `passes/techmap/dfflibmap.cc`.
2020-04-06 03:02:40 +00:00
Alberto Gonzalez
9168701881
Clean up pseudo-private member usage and simplify `passes/techmap/abc.cc`.
2020-04-05 21:31:18 +00:00
Alberto Gonzalez
64a32ead38
Clean up `passes/techmap/extract.cc`.
2020-04-05 19:36:23 +00:00
Alberto Gonzalez
5431ce694c
Clean up `passes/hierarchy/submod.cc`.
2020-04-05 04:39:54 +00:00
Alberto Gonzalez
5fedd0931c
Use newly-renamed `-push-copy` option.
2020-04-04 22:22:54 +00:00
Alberto Gonzalez
0ca3a8e94f
Improve style in `passes/sat/qbfsat.cc`.
2020-04-04 22:13:27 +00:00
Alberto Gonzalez
1db73e8dd2
Gracefully report error when module has nothing to prove.
2020-04-04 22:13:27 +00:00
Alberto Gonzalez
8f0f13cad2
Suppress `yosys-smtbmc` output unless the new `-show-smtbmc` option is provided.
2020-04-04 22:13:27 +00:00
Alberto Gonzalez
ce033a8e36
Fix handling of `-sat` and `-unsat` options when the solver returns `unknown`.
2020-04-04 22:13:26 +00:00
Alberto Gonzalez
6af8b767b4
Use `log_push()` and `log_pop()` and show the satisfiable model when `-specialize` is not specified.
...
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
2020-04-04 22:13:26 +00:00
Alberto Gonzalez
d311a80222
Clean up `qbfsat` command and fix AND-reduction of miter outputs.
2020-04-04 22:13:26 +00:00
Alberto Gonzalez
125a583c57
Use the `-duplicate` option rather than `-save` and `-load` with an explicit name.
...
Co-Authored-By: Claire Wolf <claire@symbioticeda.com>
2020-04-04 22:13:26 +00:00
Alberto Gonzalez
86fc49a9d6
Use internal `run_command()` API instead of `popen()`.
...
Co-Authored-By: Claire Wolf <claire@symbioticeda.com>
2020-04-04 22:13:26 +00:00
Alberto Gonzalez
09b2264837
Clean up manual casting.
...
Co-Authored-By: David Shah <dave@ds0.me>
2020-04-04 22:13:26 +00:00
Alberto Gonzalez
acf96b6b0b
Remove unimplemented `-timeout` option.
2020-04-04 22:13:26 +00:00
Alberto Gonzalez
bb101e0b3a
Implement the `-assume-outputs`, `-sat`, and -unsat` options for the `qbfsat` command.
2020-04-04 22:13:26 +00:00
Alberto Gonzalez
5527063f66
Add NDEBUG guards to `qbfsat` assertions.
2020-04-04 22:13:26 +00:00
Alberto Gonzalez
3a4fd4a999
Implement `-specialize-from-file` option for the `qbfsat` command.
2020-04-04 22:13:26 +00:00
Alberto Gonzalez
b9e79e0bb7
Implement `-write-solution` option for the `qbfsat` command.
2020-04-04 22:13:26 +00:00
Alberto Gonzalez
d07ac2612b
Clean up `passes/sat/qbfsat.cc`.
2020-04-04 22:13:26 +00:00
Alberto Gonzalez
437afa1f0c
Updated `yosys-smtbmc` to optionally dump raw bit strings, and fixed hole value recovery using that mode.
2020-04-04 22:13:25 +00:00
Alberto Gonzalez
a4598d64ef
Hole value recovery and specialization implementation for `qbfsat` command.
2020-04-04 22:13:25 +00:00
Alberto Gonzalez
2fff574741
Barebones implementation of `qbfsat` command.
2020-04-04 22:13:25 +00:00
Alberto Gonzalez
fb878b2a70
Initial skeleton for `qbfsat` command.
2020-04-04 22:13:25 +00:00
Alberto Gonzalez
a0416fe167
Rename `-duplicate` to `-push-copy`.
...
Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-04-04 21:26:11 +00:00
Alberto Gonzalez
409e2ac09d
Add `-duplicate` option to the `design` command.
2020-04-03 16:46:35 +00:00
whitequark
745251a31f
splitnets: skip modules with processes.
2020-04-03 11:27:19 +00:00
whitequark
e0def9e4d9
memory_map: add -attr option, to respect inference attributes.
...
Before this commit, memory_map (which is always a part of a synth
script) would always pick up any $mem cell that was not processed
by a preceding pass and lower it down to $dff/$mux cells.
This is undesirable for two reasons:
* If there is an explicit inference attribute set on a $mem cell,
e.g. (* ram_block *), then it is arguably incorrect to map such
a memory to $dff/$mux cells.
* If memory_map tries to lower a memory that was intended to
be mapped to a large BRAM, it often takes extraordinarily long
time to finish, produces an extremely large log file, and outputs
an unusable design.
After this commit, properly invoked memory_map will not map any
memory that has an explicit inference attribute specified, solving
the first issue, and alleviating the second. The default behavior
is not changed.
2020-04-03 05:51:40 +00:00
Eddie Hung
5f662b1c43
Merge pull request #1767 from YosysHQ/eddie/idstrings
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IdString: use more ID::*, make them easier to use, speed up IdString::in()
2020-04-02 11:47:25 -07:00
Eddie Hung
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
Marcin Kościelnicki
2d3753d730
iopadmap: Fix z assignment to inout port
...
Fixes #1841 .
2020-04-02 18:15:04 +02:00
Claire Wolf
22ef5701c0
Merge pull request #1842 from YosysHQ/mwk/fix-deminout-xz
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deminout: prevent any constant assignment from demoting to input
2020-04-02 18:14:34 +02:00
Eddie Hung
fdafb74eb7
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
Eddie Hung
37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup
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kernel: speedup by using more pass-by-const-ref
2020-04-02 07:13:33 -07:00
Eddie Hung
c90324662c
Merge pull request #1828 from YosysHQ/eddie/celltypes_speedup
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kernel: share a single CellTypes within a pass
2020-04-01 14:17:45 -07:00
Eddie Hung
4ae7f3a8ed
Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor
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opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs
2020-04-01 14:17:01 -07:00
Eddie Hung
e79bc45975
Merge pull request #1789 from YosysHQ/eddie/opt_expr_alu
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opt_expr: improve performance on $alu and $sub
2020-04-01 14:11:09 -07:00
Eddie Hung
1bb5a5215f
Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedup
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opt_merge: speedup
2020-03-31 14:50:32 -07:00
Eddie Hung
3e88ede061
Merge pull request #1835 from boqwxp/cleanup_sat_expose
...
Clean up pseudo-private member usage in `passes/sat/expose.cc`.
2020-03-30 13:05:12 -07:00
Eddie Hung
0d878ca256
Merge pull request #1832 from boqwxp/cleanup_passes_cmds_design
...
Clean up pseudo-private member usage in `passes/cmds/design.cc`.
2020-03-30 11:56:17 -07:00
Eddie Hung
2c0739cbad
Merge pull request #1786 from boqwxp/hierarchycc_cleanup
...
Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`.
2020-03-30 11:37:51 -07:00
Eddie Hung
9f7d20a653
Merge pull request #1831 from boqwxp/cleanup_sat_eval
...
Clean up pseudo-private member usage in `passes/sat/eval.cc`.
2020-03-30 11:13:53 -07:00
Eddie Hung
769c7318e7
Merge pull request #1833 from boqwxp/cleanup_sat_freduce
...
Clean up pseudo-private member usage in `passes/sat/freduce.cc`.
2020-03-30 11:13:06 -07:00
Alberto Gonzalez
00544cffab
Remove unused function parameter.
2020-03-30 18:00:19 +00:00
Alberto Gonzalez
5a0f029e23
Simplify iterating over selected modules or cells.
...
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
2020-03-30 17:56:07 +00:00
Alberto Gonzalez
7fc0938bb6
Replace `RTLIL::id2cstr()` with `log_id()`.
...
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-30 16:50:36 +00:00
Alberto Gonzalez
4c92f9380c
Fix double deletion in `passes/hierarchy/hierarchy.cc`.
...
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-30 16:43:54 +00:00
Alberto Gonzalez
f4faa1514b
Further clean up `passes/sat/eval.cc`.
...
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-30 16:38:35 +00:00
Alberto Gonzalez
9f265dfd3f
Further clean up `passes/sat/freduce.cc`.
...
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-30 16:25:30 +00:00
Alberto Gonzalez
696660351f
Clean up more in `passes/sat/expose.cc`.
...
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
2020-03-30 16:16:16 +00:00
Eddie Hung
1d93d1e59f
memory_share: fix stray brace
2020-03-30 08:35:40 -07:00
Eddie Hung
4d897975a8
Code review fixes
2020-03-30 08:22:46 -07:00
Eddie Hung
f64d59d824
Apply suggestions from code review
...
Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-03-30 08:19:56 -07:00
Marcin Kościelnicki
f68985f997
deminout: prevent any constant assignment from demoting to input
...
Before this patch,
```
module top(inout io);
assign io = 1'bx;
endmodule
```
would have the `io` pin demoted to input (same happens for `1'bz`,
but not for `1'b0` or `1'b1`), resulting in check failures later on.
Part of fix for #1841 .
2020-03-30 15:04:31 +02:00
N. Engelhardt
2c847e7efe
Merge pull request #1778 from rswarbrick/sv-defines
...
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-30 13:51:12 +02:00
Miodrag Milanovic
1dbc701728
Explicit include of csignal
2020-03-28 09:49:08 +01:00
Miodrag Milanovic
5cdcd6ec79
windows - there are no stopping signals
2020-03-28 09:09:11 +01:00
Alberto Gonzalez
1197a43380
Clean up pseudo-private member usage in `passes/sat/expose.cc`.
2020-03-28 06:18:09 +00:00
Alberto Gonzalez
9a0cdc3835
Clean up pseudo-private member usage in `passes/sat/freduce.cc`.
2020-03-28 06:08:23 +00:00
Alberto Gonzalez
4681f02a6e
Clean up pseudo-private member usage in `passes/cmds/design.cc`.
2020-03-28 05:10:18 +00:00
Alberto Gonzalez
b63b2dbbc3
Clean up pseudo-private member usage in `passes/sat/eval.cc`.
2020-03-28 03:11:23 +00:00
Rupert Swarbrick
044ca9dde4
Add support for SystemVerilog-style `define to Verilog frontend
...
This patch should support things like
`define foo(a, b = 3, c) a+b+c
`foo(1, ,2)
which will evaluate to 1+3+2. It also spots mistakes like
`foo(1)
(the 3rd argument doesn't have a default value, so a call site is
required to set it).
Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.
Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.
Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
2020-03-27 16:08:26 +00:00
Eddie Hung
d40f12252b
kernel: clear some more ShareWorker state
2020-03-26 15:05:45 -07:00
Claire Wolf
590d8eccb7
Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fix
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techmap: Fix cell names with _TECHMAP_REPLACE_.*
2020-03-26 19:03:37 +01:00
N. Engelhardt
3e46faa58c
Merge pull request #1763 from boqwxp/issue1762
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Closes #1762 . Adds warnings for `select` arguments not matching any object and for `add` command when no modules selected
2020-03-23 20:14:13 +01:00
Alberto Gonzalez
0da65d498b
Do not warn on empty selection with prefixed `arg_memb`.
...
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
2020-03-23 17:50:11 +00:00
Alberto Gonzalez
ca4e5dd56e
Suppress warnings for empty `select` arguments when `-count` or `-assert-*` options are set.
2020-03-23 17:30:53 +00:00
Marcin Kościelnicki
c2bf11e42a
techmap: Fix cell names with _TECHMAP_REPLACE_.*
...
Fixes #1804 .
2020-03-23 11:17:07 +01:00
N. Engelhardt
91d12f4d59
Merge pull request #1785 from boqwxp/mitercc_cleanup
...
Clean up pseudo-private member usage in `passes/sat/miter.cc`.
2020-03-23 11:10:39 +01:00
Alberto Gonzalez
5026f36250
Warn on empty selection for `add` command.
2020-03-23 05:58:12 +00:00
R. Ou
c34969d3f1
iopadmap: Attempt to give new wires/cells meaningful names
2020-03-22 23:01:09 +01:00
Eddie Hung
0c0dc4ffc3
opt_expr: fix failing $xnor test
2020-03-20 14:39:08 -07:00
Eddie Hung
af16ca9dd4
opt_expr: fix missing brace
2020-03-20 09:17:53 -07:00
Eddie Hung
01f9aabc2f
opt_expr: extend to $xnor and $_XNOR_
2020-03-19 16:56:39 -07:00
Eddie Hung
ee5995641e
opt_expr: optimise 1-bit $xor or $_XOR_ with constant input
2020-03-19 16:33:54 -07:00
Eddie Hung
8d1fa0e3b9
opt_expr: remove redundant
2020-03-19 14:34:27 -07:00
Eddie Hung
213a895589
opt_expr: optimise $sub when both A[i] and B[i] == 1'b1
2020-03-19 14:34:10 -07:00
Eddie Hung
a8e5d0c402
opt_expr: optimise for identity $alu-s just like $add/$sub
2020-03-19 14:24:55 -07:00
Marcin Kościelnicki
e91368a5f4
fsm_extract: Initialize celltypes with full design.
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Fixes #1781 .
2020-03-19 18:51:21 +01:00
N. Engelhardt
e03f725ef2
Merge pull request #1774 from boqwxp/exec
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Add `exec` command to allow running shell commands from inside Yosys scripts
2020-03-19 13:14:43 +01:00
Alberto Gonzalez
6b626c2b0f
Clean up pseudo-private member usage in `passes/sat/miter.cc`.
2020-03-19 07:07:22 +00:00
Alberto Gonzalez
b88faceced
Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`.
2020-03-19 06:49:52 +00:00
Eddie Hung
7ad7f41bc5
kernel: share a single CellTypes within a pass
2020-03-18 12:21:40 -07:00
Eddie Hung
4555b5b819
kernel: more pass by const ref, more speedups
2020-03-18 11:21:53 -07:00
Alberto Gonzalez
7ea7fb700b
Update copyright and license header.
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I hereby assign to Claire Wolf the copyright for all work I did on `passes/cmds/exec.cc`.
In the event that this copyright assignment is not legally valid, I offer this work under the ISC license.
2020-03-18 09:17:31 +00:00
Alberto Gonzalez
cbc5664d37
Clean up `exec` code according to review.
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Co-Authored-By: Miodrag Milanović <mmicko@gmail.com>
2020-03-18 09:17:12 +00:00
Claire Wolf
7f5c73d58f
Add N:* to select language, fix some old code
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-17 18:47:01 +01:00
Eddie Hung
a2fa1654dc
Merge pull request #1769 from boqwxp/select_cleanup
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Clean up code style and pseudo-private member usage in `passes/cmds/select.cc`
2020-03-17 10:43:45 -07:00
Alberto Gonzalez
9d9bbdce5d
Further clean up `passes/cmds/select.cc`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-16 20:35:19 +00:00
Alberto Gonzalez
70093698f5
Cleanup code style and pseudo-private member usage in `passes/cmds/select.cc`.
2020-03-16 20:35:11 +00:00
Eddie Hung
cdf17c4455
opt_merge: unordered_map -> dict as per @cliffordwolf review
2020-03-16 12:44:33 -07:00
Eddie Hung
9f30d7f843
opt_merge: speedup
2020-03-16 12:43:54 -07:00
Alberto Gonzalez
8ba49a8462
Allow specifying multiple regexes to match in `exec` command output, and also to specify regexes that must _not_ match.
2020-03-16 07:52:57 +00:00
Alberto Gonzalez
e6c09f1e0e
Add `exec` command to run shell commands.
2020-03-16 07:52:57 +00:00
Miodrag Milanovic
8f221118d2
Add YS_ prefix to macros, add explanation and apply to older version as well
2020-03-13 17:19:54 +01:00
Eddie Hung
432a09af80
kernel: SigSpec use more const& + overloads to prevent implicit SigSpec
2020-03-13 08:17:39 -07:00
Miodrag Milanovic
7c54e61979
Use boost xpressive for gcc 4.8
2020-03-13 14:58:35 +01:00
N. Engelhardt
6986371bac
Merge pull request #1751 from boqwxp/add_assert
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Extend `add` command to allow adding $assert cells.
2020-03-12 11:18:35 +01:00
Eddie Hung
dd8ebf7873
Merge pull request #1743 from YosysHQ/eddie/abc9_keep
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abc9: improve (* keep *) handling
2020-03-11 06:32:15 -07:00
Alberto Gonzalez
005dd601ab
Extend `add` command to allow adding cells for verification like $assert, $assume, etc.
2020-03-10 21:49:22 +00:00
David Shah
f2550d45ff
Merge pull request #1753 from YosysHQ/dave/abc9-speedup
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Add ScriptPass::run_nocheck and use for abc9
2020-03-10 13:51:59 +00:00
David Shah
ddcd87b577
Merge pull request #1721 from YosysHQ/dave/tribuf-unused
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deminout: Don't demote inouts with unused bits
2020-03-10 13:51:40 +00:00
Alberto Gonzalez
47537f2e42
Clean up passes/cmds/add.cc code style.
2020-03-10 10:37:10 +00:00
David Shah
b8abf14376
Add ScriptPass::run_nocheck and use for abc9
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Signed-off-by: David Shah <dave@ds0.me>
2020-03-09 14:34:22 +00:00
Eddie Hung
80dcc8a0d1
abc9: for sccs, create a new wire instead of using entirety of existing
2020-03-06 10:30:07 -08:00
Eddie Hung
91a7a74ac4
abc9: (* keep *) wires to be PO only, not PI as well; fix scc handling
2020-03-06 10:20:30 -08:00
Eddie Hung
2335c59e5b
abc: add abc.debug scratchpad option
2020-03-06 10:09:01 -08:00
David Shah
5cae9c6e16
deminout: Don't demote inouts with unused bits
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Signed-off-by: David Shah <dave@ds0.me>
2020-03-04 18:44:38 +00:00
Claire Wolf
879124333f
Merge pull request #1519 from YosysHQ/eddie/submod_po
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submod: several bugfixes
2020-03-03 08:19:06 -08:00
Marcelina Kościelnicka
968956badb
iopadmap: Look harder for already-present buffers. ( #1731 )
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iopadmap: Look harder for already-present buffers.
Fixes #1720 .
2020-03-02 21:40:09 +01:00
Eddie Hung
4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify
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abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
2020-03-02 12:32:27 -08:00
Eddie Hung
de3e5fcdc6
ystests: fix write_smt2_write_smt2_cyclic_dependency_fail
2020-02-28 12:33:55 -08:00
Eddie Hung
78929e8c3d
Fixes for older compilers
2020-02-27 10:17:29 -08:00
Eddie Hung
88d5997c80
abc9_ops: suppress -prep_box warning for abc9_flop
2020-02-27 10:17:29 -08:00
Eddie Hung
6bb3d9f9c0
Make TimingInfo::TimingInfo(SigBit) constructor explicit
2020-02-27 10:17:29 -08:00
Eddie Hung
9dcf204dec
TimingInfo: index by (port_name,offset)
2020-02-27 10:17:29 -08:00
Eddie Hung
7c3b4b80ea
Fix spacing
2020-02-27 10:17:29 -08:00
Eddie Hung
d6cff77751
abc9_ops: still emit delay table even box has no timing
2020-02-27 10:17:29 -08:00
Eddie Hung
683c5ce940
abc9_ops: demote lack of box timing info to warning
2020-02-27 10:17:29 -08:00
Eddie Hung
1ef1ca812b
Get rid of (* abc9_{arrival,required} *) entirely
2020-02-27 10:17:29 -08:00
Eddie Hung
a6fec9fe60
abc9_ops: use TimingInfo for -prep_{lut,box} too
2020-02-27 10:17:29 -08:00
Eddie Hung
3ea5506f81
abc9_ops: use TimingInfo for -prep_{lut,box} too
2020-02-27 10:17:29 -08:00
Eddie Hung
cda4acb544
abc9_ops: add and use new TimingInfo struct
2020-02-27 10:17:29 -08:00
Eddie Hung
e22fee6cdd
abc9_ops: ignore (* abc9_flop *) if not '-dff'
2020-02-27 10:17:29 -08:00
Eddie Hung
7c92b6852f
abc9_ops: sort LUT delays to be ascending
2020-02-27 10:17:29 -08:00
Eddie Hung
7317521c6f
abc9_ops: output LUT area
2020-02-27 10:17:29 -08:00
Eddie Hung
0ed550d83c
abc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto-gen small LUTs
2020-02-27 10:17:29 -08:00
Eddie Hung
12d70ca8fb
xilinx: improve specify functionality
2020-02-27 10:17:29 -08:00
Eddie Hung
577545488a
xilinx: use specify blocks in place of abc9_{arrival,required}
2020-02-27 10:17:29 -08:00
Eddie Hung
0e7c55e2a7
Auto-generate .box/.lut files from specify blocks
2020-02-27 10:17:29 -08:00
Eddie Hung
3d6603792d
abc9_ops: assert on $specify2 properties
2020-02-27 10:17:29 -08:00
Eddie Hung
74f49b1f55
abc9_ops: -prep_box, to be called once
2020-02-27 10:17:29 -08:00
Eddie Hung
5643c1b8c5
abc9_ops: -prep_lut and -write_lut to auto-generate LUT library
2020-02-27 10:17:29 -08:00
Claire Wolf
ab8826ae36
Merge pull request #1709 from rqou/coolrunner2_counter
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Improve CoolRunner-II optimization by using extract_counter pass
2020-02-27 19:05:56 +01:00
Miodrag Milanović
036c46de1e
Merge pull request #1705 from YosysHQ/logger_pass
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Logger pass
2020-02-26 13:32:49 +01:00
Miodrag Milanovic
48eed2860c
Fix line endings
2020-02-23 10:05:21 +01:00
Miodrag Milanovic
010d651450
Update explanation for expect-no-warnings
2020-02-22 10:53:23 +01:00
Miodrag Milanovic
596bb2d443
Check other regex parameters
2020-02-22 10:31:56 +01:00
Alberto Gonzalez
750e7a9a54
Closes #1714 . Fix make failure when NDEBUG=1.
2020-02-22 06:29:11 +00:00
Eddie Hung
760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve
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Improve specify parser
2020-02-21 09:15:17 -08:00
Miodrag Milanovic
419e67c170
check for regex errors
2020-02-20 11:41:37 +01:00
Eddie Hung
1d401a7991
clean: ignore specify-s inside cells when determining whether to keep
2020-02-19 10:45:10 -08:00
Miodrag Milanovic
5641b0248f
Option to expect no warnings
2020-02-17 15:36:06 +01:00
R. Ou
fec7dc5c9e
extract_counter: Implement extracting up counters
2020-02-17 03:08:52 -08:00
R. Ou
940bab6841
extract_counter: Add support for inverted clock enable
2020-02-17 03:08:52 -08:00
R. Ou
5fc180ed2d
extract_counter: Fix clock enable
2020-02-17 03:08:52 -08:00
R. Ou
12fa4a3121
extract_counter: Fix outputting count to module port
2020-02-17 03:08:52 -08:00
R. Ou
508f1ff6a1
extract_counter: Allow forbidding async reset
2020-02-17 03:08:52 -08:00
R. Ou
7b922c0d89
extract_counter: Refactor out extraction settings into struct
2020-02-17 03:08:52 -08:00
Tim 'mithro' Ansell
b9dfdbbfee
show: Add -nobg argument.
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Makes yosys wait for the viewer command to finish before continuing.
2020-02-15 14:03:16 +01:00
Eddie Hung
f9f86fd758
Revert "abc9: fix abc9_arrival for flops"
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This reverts commit f7c0dbecee
.
2020-02-14 16:08:04 -08:00
Miodrag Milanovic
31b7a9c312
Add expect option to logger command
2020-02-14 12:21:16 +01:00
Eddie Hung
0cf7598cd6
Merge pull request #1700 from YosysHQ/eddie/abc9_fixes
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Use (* abc9_init *) attribute, fix use of abc9_arrival for flops
2020-02-13 17:32:54 -08:00
Eddie Hung
3d2a2e8799
iopadmap: fixes as suggested by @mwkmwkmwk
2020-02-13 14:57:06 -08:00
Eddie Hung
f7c0dbecee
abc9: fix abc9_arrival for flops
2020-02-13 12:34:09 -08:00
Eddie Hung
00d41905df
abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr
2020-02-13 12:33:58 -08:00
Eddie Hung
ebb11bcea4
iopadmap: move \init attributes from outpad output to its input
2020-02-13 12:05:14 -08:00
Miodrag Milanovic
0ba2a2b1fa
Add new logger pass
2020-02-13 13:35:29 +01:00
Eddie Hung
c244b27b6d
abc9: cleanup
2020-02-10 10:17:23 -08:00
Eddie Hung
e6bb7b0782
Fix misc.abc9.abc9_abc9_luts
2020-02-07 08:27:45 -08:00
whitequark
60f047f136
memory_bram: add `attr_icase` option.
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Some vendor toolchains use case insensitive matching for values of
attributes that control BRAM inference.
2020-02-06 14:58:20 +00:00
Eddie Hung
505557e93e
Merge pull request #1576 from YosysHQ/eddie/opt_merge_init
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opt_merge: discard \init of '$' cells with 'Q' port when merging
2020-02-05 14:56:26 -08:00
Eddie Hung
0b308c6835
abc9_ops: -reintegrate to use derived_type for box_ports
2020-02-05 14:46:48 -08:00
Eddie Hung
5ebdc0f8e0
Merge pull request #1638 from YosysHQ/eddie/fix1631
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clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
2020-02-05 19:31:18 +01:00
Eddie Hung
0671ae7d79
Merge pull request #1661 from YosysHQ/eddie/abc9_required
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abc9: add support for required times
2020-02-05 18:59:40 +01:00
Marcelina Kościelnicka
34d2fbd2f9
Add opt_lut_ins pass. ( #1673 )
2020-02-03 14:57:17 +01:00
David Shah
4bfd2ef4f3
sv: Improve handling of wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
7e741714df
hierarchy: Correct handling of wildcard port connections with default values
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
5df591c023
hierarchy: Resolve SV wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
1055b6b1dd
Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly
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synth_xilinx: add -dsp-multonly
2020-02-02 14:53:32 +00:00
David Shah
65716c9982
xilinx_dsp: Add multonly scratchpad var to bypass
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-01 15:30:43 +00:00
Eddie Hung
136842b1ef
Merge branch 'master' into eddie/submod_po
2020-02-01 02:14:19 -08:00
Gabriel Somlo
8106c3d31b
abc9: restore ability to use ABCEXTERNAL
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-01-30 15:12:43 -05:00
Claire Wolf
1679682fa3
Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys
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Also some minor fixes to the original PR.
2020-01-29 17:01:24 +01:00
Claire Wolf
4d0118d0c1
Merge pull request #1662 from YosysHQ/dave/opt-reduce-move-check
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opt_reduce: Call check() per run rather than per optimised cell
2020-01-29 15:27:11 +01:00
Eddie Hung
a855f23f22
Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init
2020-01-28 12:46:18 -08:00
Eddie Hung
7939727d14
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts
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Unpermute LUT ordering for ice40/ecp5/xilinx
2020-01-28 11:55:51 -08:00
Claire Wolf
4ddaa70fd6
Merge pull request #1567 from YosysHQ/eddie/sat_init_warning
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sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
2020-01-28 17:40:28 +01:00
N. Engelhardt
086c133ea5
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate
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synth_xilinx: error out if tristate without '-iopad'
2020-01-28 17:24:54 +01:00
David Shah
6fd9cae5ca
opt_reduce: Call check() per run rather than per optimised cell
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Signed-off-by: David Shah <dave@ds0.me>
2020-01-28 09:42:01 +00:00
Pepijn de Vos
409e532433
redirect fuser stderr to /dev/null
2020-01-28 10:02:41 +01:00
Eddie Hung
21ce1b37fb
abc9_ops: -check for negative arrival/required times
2020-01-27 14:22:46 -08:00
Eddie Hung
e18aeda7ed
Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
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Just like Verilog...
2020-01-27 14:02:13 -08:00
Eddie Hung
48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
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Refactor `abc9` pass
2020-01-27 13:29:15 -08:00
Eddie Hung
f2576c096c
Merge branch 'eddie/abc9_refactor' into eddie/abc9_required
2020-01-27 12:29:28 -08:00
Eddie Hung
9009b76a69
abc9_ops: add comments
2020-01-27 11:18:21 -08:00
Eddie Hung
b178761551
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
2020-01-24 11:59:48 -08:00
Eddie Hung
dbf351390e
abc9: -reintegrate recover type from existing cell, check against boxid
2020-01-23 22:45:34 -08:00
Eddie Hung
245873d42d
abc9: warning message if no modules selected
2020-01-23 19:08:51 -08:00
Eddie Hung
f180dba753
abc9_ops: -prep_xaiger to skip (* keep *) cells
2020-01-23 18:56:06 -08:00
Eddie Hung
1d4314d888
abc9_ops -prep_dff: insert async s/r mux in holes when replacing $_DFF_*
2020-01-23 14:58:56 -08:00
Eddie Hung
af0e7637a2
alumacc: undo accidental commit
2020-01-22 20:54:03 -08:00
Eddie Hung
8eb5bb258c
Merge remote-tracking branch 'origin/eddie/abc9_fixes' into eddie/abc9_refactor
2020-01-22 12:30:14 -08:00
Eddie Hung
a94b41011d
abc9: error out if flip-flop init is 1'b1 for '-dff'
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Due to ABC sequential synthesis restriction
2020-01-22 10:08:48 -08:00
Eddie Hung
3b44b53e94
abc9: fix scratchpad entry abc9.verify
2020-01-22 09:36:54 -08:00
Eddie Hung
3d9737c1bd
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-21 16:27:40 -08:00
Claire Wolf
5791c52e1b
Merge pull request #1637 from YosysHQ/mwk/fix-1634
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fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.
2020-01-21 18:37:06 +01:00
Claire Wolf
f165a74824
Merge pull request #1621 from YosysHQ/clifford/fminit
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Add fminit pass
2020-01-20 22:01:57 +01:00
Eddie Hung
6a163b5ddd
xilinx_dsp: another typo; move xilinx specific test
2020-01-17 17:07:03 -08:00
Eddie Hung
db68e4c2a7
ice40_dsp: fix typo
2020-01-17 16:08:04 -08:00
Eddie Hung
e17f3f8c63
Consistency
2020-01-17 16:06:20 -08:00
Eddie Hung
ee500b6d8e
xilinx_dsp: add parameter defaults
2020-01-17 16:05:10 -08:00
Eddie Hung
4985318263
ice40_dsp: add default values for parameters
2020-01-17 15:37:52 -08:00
Eddie Hung
6692e5d558
ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputs
2020-01-17 15:28:02 -08:00
Eddie Hung
d4e188299b
abc9: add some log_{push,pop}() as per @nakengelhardt
2020-01-17 12:00:14 -08:00
Eddie Hung
5a63c19747
abc9_ops: -write_box is empty, output a dummy box to prevent ABC error
2020-01-15 13:14:48 -08:00
Eddie Hung
e30b6bbbf8
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
2020-01-15 09:51:31 -08:00
Eddie Hung
485e08e436
abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *)
2020-01-14 16:33:41 -08:00
Eddie Hung
f60e071e1c
abc9_ops: -check to check abc9_{arrival,required}
2020-01-14 15:24:44 -08:00
Eddie Hung
1c88a6c240
abc9_ops: implement a requireds_cache
2020-01-14 15:20:04 -08:00
Eddie Hung
0e4285ca0d
abc9_ops: generate flop box ids, add abc9_required to FD* cells
2020-01-14 15:05:49 -08:00
Eddie Hung
588a713b54
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-14 14:28:07 -08:00
Eddie Hung
4656f202c6
abc9_ops: -reintegrate to not trim box padding anymore
2020-01-14 14:27:29 -08:00
Eddie Hung
b951ca9e1c
abc9_ops: fix -reintegrate handling of $__ABC9_DELAY
2020-01-14 14:06:02 -08:00
Marcin Kościelnicki
a5d2358a60
fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.
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Fixes #1634 .
2020-01-14 22:49:20 +01:00
Eddie Hung
ec95fbb273
abc9_ops: -prep_times -> -prep_delays; add doc
2020-01-14 13:21:58 -08:00
Eddie Hung
593897ffc0
abc9_ops: cleanup
2020-01-14 13:13:15 -08:00
Eddie Hung
300003cb78
abc9_ops: discard $__ABC9_DELAY boxes
2020-01-14 13:09:54 -08:00
Eddie Hung
915e7dde73
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-14 12:57:56 -08:00
Eddie Hung
654247abe9
abc9_ops/write_xaiger: update doc
2020-01-14 12:40:36 -08:00
Eddie Hung
468386d67d
abc9_ops: -prep_holes -> -prep_xaiger, move padding to write_xaiger
2020-01-14 12:25:45 -08:00
Eddie Hung
53a99ade9c
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-14 11:46:56 -08:00
Eddie Hung
61ffd2d199
Merge pull request #1633 from YosysHQ/eddie/fix_autoname
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autoname: do not rename ports
2020-01-14 11:40:54 -08:00
Eddie Hung
de969adcd8
autoname: do not autoname ports
2020-01-14 10:13:29 -08:00
Eddie Hung
531fddf797
abc9_ops: -break_scc -> -mark_scc using (* keep *), remove -unbreak_scc
2020-01-13 23:42:27 -08:00
Eddie Hung
b678b15c6d
abc9_ops: ignore inouts of all cell outputs for topo ordering
2020-01-13 23:33:37 -08:00
Eddie Hung
2c65e1abac
abc9: break SCC by setting (* keep *) on output wires
2020-01-13 21:45:27 -08:00
Eddie Hung
a2c4d98da7
abc9: add -run option
2020-01-13 19:22:23 -08:00
Eddie Hung
a6d4ea7463
abc9: respect (* keep *) on cells
2020-01-13 19:21:11 -08:00
Eddie Hung
766e16b525
read_aiger: make $and/$not/$lut the prefix not suffix
2020-01-13 17:34:37 -08:00
Eddie Hung
808b388e34
abc9: log which module is being operated on
2020-01-13 09:43:57 -08:00
Eddie Hung
9f3cb981d7
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-13 09:22:42 -08:00
Eddie Hung
f9aae90e7a
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-12 15:19:41 -08:00
Eddie Hung
295e241c07
cleanup
2020-01-11 17:28:24 -08:00
Eddie Hung
79db12f238
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-11 17:26:25 -08:00
Eddie Hung
556ed0e18a
MIssed this merge conflict
2020-01-11 17:05:30 -08:00
Eddie Hung
c063436eea
Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpad
2020-01-11 17:02:20 -08:00
Eddie Hung
11128dccb5
Merge branch 'eddie/abc9_refactor' of github.com:YosysHQ/yosys into eddie/abc9_refactor
2020-01-11 13:56:41 -08:00
Eddie Hung
c820682314
abc9: fix help message, found by @nakengelhardt
2020-01-11 12:11:35 -08:00
Eddie Hung
784fec93c9
abc9: cleanup
2020-01-11 08:42:58 -08:00
Eddie Hung
45d9caf3f9
abc9: remove -nomfs option
2020-01-11 08:08:35 -08:00
Eddie Hung
f24de88f38
log_debug() for abc9_{arrival,required} times
2020-01-10 17:13:27 -08:00
Eddie Hung
ed2aeb498e
Copy-pasta
2020-01-10 15:09:42 -08:00
Eddie Hung
291530c59f
abc9: add abc9.verify and abc9.debug options
2020-01-10 15:04:13 -08:00
Eddie Hung
475d983676
abc9_ops -prep_times: generate flop boxes from abc9_required attr
2020-01-10 14:49:52 -08:00
Eddie Hung
e0af812180
abc9_ops -prep_times: update comment
2020-01-10 12:38:49 -08:00
Eddie Hung
b2259a9201
Add abc9_ops -check, -prep_times, -write_box for required times
2020-01-10 11:45:41 -08:00
Eddie Hung
1f7893bd8c
abc9: fix memory leak
2020-01-10 10:46:06 -08:00
Eddie Hung
d1f8371481
abc9: fix typos
2020-01-10 10:00:09 -08:00
Eddie Hung
e378902f93
Tune abc9.script.flow
2020-01-09 18:16:58 -08:00
Eddie Hung
8b6309747b
Add '-v' to &if for abc9.script.default.fast
2020-01-09 17:49:56 -08:00
Eddie Hung
32946a402d
abc9: start post-fix with semicolon
2020-01-09 17:35:13 -08:00
Eddie Hung
ca70f96503
abc9.script.* constpad entries to start with '+'
2020-01-09 17:17:47 -08:00
Eddie Hung
ef3e84aac9
Revert "abc9: if -script value is a file, then source it, otherwise commands"
...
This reverts commit 0696b7bc9e
.
2020-01-09 17:11:09 -08:00
Eddie Hung
67c9c41f7e
Move abc9.* constpad entries to Abc9Pass::on_register()
2020-01-09 17:10:54 -08:00
Eddie Hung
5e280a3b59
abc9_exe: -box to not require -lut
2020-01-09 14:04:10 -08:00
Clifford Wolf
3fa374a698
Add fminit pass
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2020-01-09 21:22:54 +01:00
Eddie Hung
4e396ee7a3
abc9_ops: fix reintegration by removing optimised-away boxes
2020-01-09 11:21:03 -08:00
Eddie Hung
589ffead5c
scratchpad entry abc9.if.R to &if -R
2020-01-08 12:13:06 -08:00
Eddie Hung
0696b7bc9e
abc9: if -script value is a file, then source it, otherwise commands
2020-01-08 12:11:55 -08:00
Eddie Hung
050f03f15b
abc9: add time as last script command
2020-01-08 10:55:44 -08:00
Eddie Hung
e230fd8afe
Fix {C} substitution
2020-01-08 10:52:08 -08:00
Eddie Hung
a63e2508fc
Add RTLIL::constpad, init by yosys_setup(); use for abc9
2020-01-08 10:52:08 -08:00
Eddie Hung
88f14b8bca
Cleanup
2020-01-08 10:02:45 -08:00
Eddie Hung
8a47e6ddfd
Fix abc9 help, add labels
2020-01-08 10:00:50 -08:00
Eddie Hung
102f139728
scc to use design->selected_modules() which avoids black/white-boxes
2020-01-07 15:46:36 -08:00
Eddie Hung
dc3b21c1c0
abc9_ops -reintegrate: process box connections
2020-01-07 09:48:57 -08:00
Eddie Hung
6e12ba218b
Fix tabs and cleanup
2020-01-07 09:32:58 -08:00
Eddie Hung
5d9050a955
abc_exe: move 'count_outputs' check to abc
2020-01-07 08:00:32 -08:00
Eddie Hung
cf3a13746d
Add abc9_ops -reintegrate; moved out from now abc9_exe
2020-01-06 15:52:59 -08:00
Eddie Hung
46ed507b93
abc9_map: drop padding in box connections
2020-01-06 15:14:54 -08:00
Eddie Hung
1e2ab19f42
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2020-01-06 15:05:08 -08:00
Eddie Hung
98ee8c14df
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-06 15:02:44 -08:00
Eddie Hung
aa58472a29
Revert "write_xaiger to pad, not abc9_ops -prep_holes"
...
This reverts commit b5f60e055d
.
2020-01-06 13:34:45 -08:00
Eddie Hung
2bf442ca01
Cleanup
2020-01-06 13:02:04 -08:00
Eddie Hung
b70e87137d
scc to use design->selected_modules() which avoids black/white-boxes
2020-01-06 12:36:11 -08:00
Eddie Hung
4f13ab823f
Revert "scc command to ignore blackboxes"
...
This reverts commit 32695e5032
.
2020-01-06 12:29:13 -08:00
Eddie Hung
36ae2e52e4
Fix bad merge
2020-01-06 12:28:58 -08:00
Eddie Hung
6728a62d92
abc9: uncomment nothing to map message
2020-01-06 12:21:50 -08:00
Eddie Hung
921ff0f5e3
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2020-01-06 12:04:08 -08:00
Eddie Hung
64ace4b0dc
Fixes
2020-01-06 11:53:48 -08:00
Eddie Hung
d152fe961f
Fixes
2020-01-06 11:50:55 -08:00
Eddie Hung
275e937fc1
abc9: remove -markgroups option, since operates on fully selected mod
2020-01-06 10:43:21 -08:00
Eddie Hung
1cf974ff40
abc9: cleanup
2020-01-06 10:26:49 -08:00
N. Engelhardt
fcc1c14adc
error if multiple -g options are given for abc
2020-01-06 19:10:13 +01:00
Eddie Hung
f576721a37
Add abc9.dff scratchpad option
2020-01-06 09:46:02 -08:00
Eddie Hung
45f87bb8ad
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-06 09:44:17 -08:00
N. Engelhardt
7764b62d23
check scratchpad for arguments in abc pass too
2020-01-06 10:46:44 +01:00
N. Engelhardt
b376548fb9
inherit default values when checking scratchpad for arguments
2020-01-06 10:46:10 +01:00
Eddie Hung
b5f60e055d
write_xaiger to pad, not abc9_ops -prep_holes
2020-01-05 10:20:24 -08:00
Eddie Hung
8293a3fe74
Cleanup
2020-01-04 09:30:48 -08:00
Eddie Hung
6556a1347a
Fix when -dff not given
2020-01-04 09:17:01 -08:00
Eddie Hung
930f03e883
Call -prep_holes before aigmap; fix topo ordering
2020-01-03 15:38:18 -08:00
Eddie Hung
a819656972
WIP
2020-01-03 14:59:55 -08:00
Eddie Hung
559f3379e8
Preserve topo ordering from -prep_holes to write_xaiger
2020-01-03 14:37:58 -08:00
Eddie Hung
bb70915fb8
WIP
2020-01-03 13:21:56 -08:00
Eddie Hung
e1f494ab1d
WIP
2020-01-03 13:08:52 -08:00
N. Engelhardt
b2ad781b07
share codepath for scratchpad argument handling with command arguments
2020-01-03 14:11:41 +01:00
N. Engelhardt
341fd872b5
Merge branch 'master' of https://github.com/YosysHQ/yosys into abc_scratchpad_script
2020-01-03 12:28:48 +01:00
Eddie Hung
a050f9c808
Remove a few log_{push,pop}()
2020-01-02 16:14:04 -08:00
Eddie Hung
4eaf415052
aigmap everything
2020-01-02 16:13:44 -08:00
Eddie Hung
32695e5032
scc command to ignore blackboxes
2020-01-02 16:06:39 -08:00
Eddie Hung
7fe268fcdb
Move scc operations out of inner loop
2020-01-02 16:00:26 -08:00
Eddie Hung
222e5e58ad
Cleanup
2020-01-02 15:58:45 -08:00
Eddie Hung
c28bea0382
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2020-01-02 15:57:35 -08:00
Eddie Hung
5f97086302
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-02 15:14:12 -08:00
Eddie Hung
b454735bea
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-02 12:44:06 -08:00
Eddie Hung
ca42af56a4
Update doc
2020-01-02 12:41:57 -08:00
Eddie Hung
8e507bd807
abc9 -keepff -> -dff; refactor dff operations
2020-01-02 12:36:54 -08:00
Eddie Hung
d6242be802
Merge pull request #1601 from YosysHQ/eddie/synth_retime
...
"abc -dff" to no longer retime by default
2020-01-02 08:46:24 -08:00
Eddie Hung
6dc63e84ef
Cleanup abc9, update doc for -keepff option
2020-01-01 08:34:57 -08:00
Eddie Hung
c40b1aae42
Restore abc9 -keepff
2020-01-01 08:34:43 -08:00
Eddie Hung
ac808c5e2a
attributes.count() -> get_bool_attribute()
2020-01-01 08:33:32 -08:00
Miodrag Milanovic
e0c879684f
take skip wire bits into account
2020-01-01 16:13:14 +01:00
Eddie Hung
96db05aaef
parse_xaiger to not take box_lookup
2019-12-31 17:06:03 -08:00
Eddie Hung
cac7f5d82e
Do not re-order carry chain ports, just precompute iteration order
2019-12-31 16:12:40 -08:00
Eddie Hung
dacdc6cc94
Remove abc9 -clk option
2019-12-30 22:59:14 -08:00
Eddie Hung
f1bf44ae8f
abc9_ops -prep_dff cope with lack of holes module
2019-12-30 22:58:39 -08:00
Eddie Hung
a367f703ea
Rename struct
2019-12-30 22:56:19 -08:00
Eddie Hung
fad99c2ec7
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2019-12-30 20:14:24 -08:00
Eddie Hung
b42b64e8ed
Move Pass::call() out of abc9_ops into abc9
2019-12-30 19:23:54 -08:00
Eddie Hung
52f649dcfd
Use function arg
2019-12-30 18:47:06 -08:00
Eddie Hung
0317a2b476
holes_module to be whitebox
2019-12-30 18:46:22 -08:00
Eddie Hung
b50de28c04
Add abc9_ops -prep_holes
2019-12-30 18:00:49 -08:00
Eddie Hung
16c4ec7eda
Add abc9_ops -prep_dff
2019-12-30 16:36:33 -08:00
Eddie Hung
88b9c8d46d
Restore count_outputs, move process check to abc
2019-12-30 16:29:08 -08:00
Eddie Hung
dbffbeef5c
Fix struct name
2019-12-30 16:21:20 -08:00
Eddie Hung
7649ec72c9
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2019-12-30 16:20:58 -08:00
Eddie Hung
4c3f517425
Remove delay targets doc
2019-12-30 16:11:42 -08:00
Eddie Hung
658f424d7d
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2019-12-30 16:01:38 -08:00
Eddie Hung
0735572934
write_xaiger to use scratchpad for stats; cleanup abc9
2019-12-30 15:35:33 -08:00
Eddie Hung
22fe931c86
Grammar
2019-12-30 15:07:15 -08:00
Eddie Hung
fc4b8b8991
Remove submod changes
2019-12-30 14:56:14 -08:00
Eddie Hung
405e974fe5
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-30 14:31:42 -08:00
Eddie Hung
d7ada66497
Add "synth_xilinx -dff" option, cleanup abc9
2019-12-30 14:13:16 -08:00
Eddie Hung
566d9fb77f
Revert "ABC to call retime all the time"
...
This reverts commit 9aa94370a5
.
2019-12-30 13:28:29 -08:00
Eddie Hung
52a27700e2
Grammar
2019-12-30 12:26:39 -08:00
Eddie Hung
f348ffa44d
abc9_techmap -> _map; called from abc9 script pass along with abc9_ops
2019-12-28 05:07:46 -08:00
Eddie Hung
ec25394808
Rename abc9.cc -> abc9_techmap.cc
2019-12-28 03:16:28 -08:00
Miodrag Milanovic
3e14ff1667
fixed invalid char
2019-12-25 20:38:48 +01:00
Marcin Kościelnicki
a24596def3
iopadmap: Emit tristate buffers with const OE for some edge cases.
2019-12-25 17:37:58 +01:00
Marcin Kościelnicki
e226a8f7f1
Minor nit fixes
2019-12-25 15:39:40 +01:00
Eddie Hung
1d0ac659ad
Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too
2019-12-23 14:40:59 -08:00
Eddie Hung
75acaff6f5
Fix CEA/CEB check
2019-12-23 14:22:13 -08:00
Eddie Hung
edabe73377
Fix checking CE[AB] and for direct connections
2019-12-23 13:41:26 -08:00
Eddie Hung
71cac30309
Support unregistered cascades for A and B inputs
2019-12-23 12:38:18 -08:00
Eddie Hung
d00533eaa8
Add DSP48A* PCOUT -> PCIN cascade support
2019-12-23 11:42:46 -08:00
Eddie Hung
509070f82f
Disable clock domain partitioning in Yosys pass, let ABC do it
2019-12-23 08:36:20 -08:00
Marcin Kościelnicki
666c6128a9
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
Eddie Hung
1ea1e8e54f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 13:56:13 -08:00
Eddie Hung
1482f32d53
Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut
...
Interpret "abc9 -lut" as lut string only if [0-9:]
2019-12-20 13:09:00 -08:00
Eddie Hung
f5e0a07ad6
Add $_FF_ and $_SR* courtesy of @mwkmwkmwk
2019-12-20 13:00:04 -08:00
Eddie Hung
d038cea3c7
More stringent check for flop cells
2019-12-20 12:32:00 -08:00
Eddie Hung
979bf36fb0
Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t
2019-12-19 11:23:41 -08:00
Eddie Hung
94f15f023c
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-19 10:29:40 -08:00
Eddie Hung
269ba56a6d
Merge pull request #1581 from YosysHQ/clifford/fix1565
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Fix sim for assignments with lhs<rhs size
2019-12-19 12:24:27 -05:00
Eddie Hung
3b559de6e9
Interpret "abc9 -lut" as lut string only if [0-9:]
2019-12-18 12:21:12 -08:00
Eddie Hung
d0afe4e10d
Merge branch 'master' of github.com:YosysHQ/yosys
2019-12-18 12:08:38 -08:00
Eddie Hung
b2a42e1fac
Merge pull request #1572 from nakengelhardt/scratchpad_pass
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add a command to read/modify scratchpad contents
2019-12-18 13:55:44 -05:00
Marcin Kościelnicki
a235250403
xilinx: Add xilinx_dffopt pass ( #1557 )
2019-12-18 13:43:43 +01:00
N. Engelhardt
3671ecc7d0
use extra_args
2019-12-18 12:30:30 +01:00
Eddie Hung
c9c77a90b3
Remove &verify -s
2019-12-17 16:11:54 -08:00
Eddie Hung
b1b99e421e
Use pool<> instead of std::set<> to preserver ordering
2019-12-17 16:10:40 -08:00
N. Engelhardt
c8bc1793a4
check scratchpad variable abc9.scriptfile
2019-12-17 19:39:55 +01:00
Clifford Wolf
41ed6ca7a5
Fix sim for assignments with lhs<rhs size, fixes #1565
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-12-17 17:36:30 +01:00
Eddie Hung
dccd7eb39f
Cleanup
2019-12-17 00:25:08 -08:00
Eddie Hung
33e6d05585
Enforce non-existence
2019-12-16 17:06:30 -08:00
Eddie Hung
d9bf7061cd
Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop
2019-12-16 16:49:48 -08:00
Eddie Hung
187e1c46e6
Update doc
2019-12-16 14:48:53 -08:00
Eddie Hung
4158ce4eda
More sloppiness, thanks @dh73 for spotting
2019-12-16 13:56:45 -08:00
Eddie Hung
6b384861e4
Oops
2019-12-16 13:31:05 -08:00
Eddie Hung
503d1db551
Implement 'attributes' grammar
2019-12-16 12:58:13 -08:00
Eddie Hung
952d62991f
Merge branch 'diego/memattr' of https://github.com/dh73/yosys into diego/memattr
2019-12-16 12:07:49 -08:00
Diego H
87e21b0122
Fixing compiler warning/issues. Moving test script to the correct place
2019-12-16 10:23:45 -06:00
N. Engelhardt
abcd82daca
add assert option to scratchpad command
2019-12-16 14:00:21 +01:00
Diego H
b35559fc33
Merging attribute rules into a single match block; Adding tests
2019-12-15 23:33:09 -06:00
Alyssa Milburn
e709fd3da1
Fix opt_expr.eqneq.cmpzero debug print
2019-12-15 20:40:38 +01:00
Diego H
266993408a
Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific
2019-12-13 15:43:24 -06:00
Eddie Hung
83d36394f8
opt_merge to discard \init of '$' cells with 'Q' port when merging
2019-12-13 10:26:37 -08:00
N. Engelhardt
91f427d719
check scratchpad variables for custom abc scripts
2019-12-13 12:54:52 +01:00
N. Engelhardt
ce3615b367
add periods and newlines to help message
2019-12-13 10:28:34 +01:00
Eddie Hung
bea15b537b
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-12 14:57:17 -08:00
Eddie Hung
abf99d4dae
tribuf: set scratchpad boolean 'tribuf.added_something'
2019-12-12 14:32:29 -08:00
N. Engelhardt
1187e91c2f
add test and make help message more verbose
2019-12-12 20:51:59 +01:00
N. Engelhardt
4c7cda1c8b
add a command to read/modify scratchpad contents
2019-12-12 16:25:03 +01:00
Eddie Hung
9a892199f7
Suppress warning message for init[i] = 1'bx
2019-12-11 11:27:10 -08:00
Eddie Hung
7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
...
Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
2019-12-09 17:38:48 -08:00
Eddie Hung
36a88be609
ice40_wrapcarry -unwrap to preserve 'src' attribute
2019-12-09 14:28:54 -08:00
Eddie Hung
bbdf2452b3
-unwrap to create $lut not SB_LUT4 for opt_lut
2019-12-09 13:27:09 -08:00
Eddie Hung
500ed9b501
Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4
2019-12-09 12:45:22 -08:00
Eddie Hung
e05372778a
ice40_wrapcarry to really preserve attributes via -unwrap option
2019-12-09 11:48:28 -08:00
Eddie Hung
a46a7e8a67
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-06 23:22:52 -08:00
Eddie Hung
946d5854c0
Drop keep=0 attributes on SB_CARRY
2019-12-06 17:27:47 -08:00
Eddie Hung
ab667d3d47
Call abc9 with "&write -n", and parse_xaiger() to cope
2019-12-06 16:35:57 -08:00
Eddie Hung
fce527f4f7
Fix abc9 re-integration, remove abc9_control_wire, use cell->type as
...
as part of clock domain for mergeability class
2019-12-06 16:20:18 -08:00
Eddie Hung
01a3cc29ba
abc9 to do clock partitioning again
2019-12-05 17:26:22 -08:00
Eddie Hung
02786b0aa0
Remove clkpart
2019-12-05 17:25:26 -08:00
Eddie Hung
a7e0cca480
Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER
2019-12-05 07:01:18 -08:00
Marcin Kościelnicki
2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. ( #1527 )
...
The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
2019-12-04 08:44:08 +01:00
Eddie Hung
d66d06b91d
Add assertion
2019-12-03 19:21:42 -08:00
Eddie Hung
a181ff66d3
Add abc9_init wire, attach to abc9_flop cell
2019-12-03 18:47:09 -08:00
Eddie Hung
5897b918b3
ice40_wrapcarry to preserve SB_CARRY's attributes
2019-12-03 14:48:11 -08:00
Eddie Hung
a265a84632
Use pool instead of std::set for determinism
2019-12-02 01:28:28 -08:00
Eddie Hung
6398b7c17c
Cleanup
2019-12-01 23:43:28 -08:00
Eddie Hung
1d87488795
Use pool instead of std::set for determinism
2019-12-01 23:26:17 -08:00
Eddie Hung
4ac1b92df3
Use pool<> not std::set<> for determinism
2019-12-01 23:19:32 -08:00
David Shah
e9ce4e658b
abc9: Fix breaking of SCCs
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Signed-off-by: David Shah <dave@ds0.me>
2019-12-01 20:44:56 +00:00
Eddie Hung
a26c52394f
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-28 12:58:30 -08:00
Eddie Hung
b3a66dff7c
Move \init signal for non-port signals as long as internally driven
2019-11-28 12:57:36 -08:00
Eddie Hung
130d3b9639
Fix multiple driver issue
2019-11-27 13:23:31 -08:00
Eddie Hung
ac5b5e97bc
Fix multiple driver issue
2019-11-27 13:21:59 -08:00
Eddie Hung
4bac6b13be
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-27 10:17:10 -08:00
Eddie Hung
cd2af66099
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-27 08:19:13 -08:00
Eddie Hung
1c0ee4f786
Do not replace constants with same wire
2019-11-27 08:18:41 -08:00
Eddie Hung
6464dc35ec
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
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xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
2019-11-27 08:00:22 -08:00
Clifford Wolf
41e0ddf4f4
Merge pull request #1501 from YosysHQ/dave/mem_copy_attr
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memory_collect: Copy attr from RTLIL::Memory to cell
2019-11-27 11:25:23 +01:00
Eddie Hung
6338615aa1
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-27 01:02:16 -08:00
Eddie Hung
c7aa2c6b79
Cleanup
2019-11-27 01:01:24 -08:00
Eddie Hung
cb05fe0f70
Check for nullptr
2019-11-27 00:51:39 -08:00
Eddie Hung
d960feeeb0
Stray log_dump
2019-11-27 00:50:25 -08:00
Eddie Hung
8c813632b6
Revert "submod to bitty rather bussy, for bussy wires used as input and output"
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This reverts commit cba3073026
.
2019-11-27 00:48:22 -08:00
Eddie Hung
969f511415
Promote output wires in sigmap so that can be detected
2019-11-26 23:39:14 -08:00
Eddie Hung
5e487b103c
Fix submod -hidden
2019-11-26 23:26:25 -08:00
Eddie Hung
435d33c373
Add -hidden option to submod
2019-11-26 23:26:12 -08:00
Marcin Kościelnicki
fdcbda195b
opt_share: Fix handling of fine cells.
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Fixes #1525 .
2019-11-27 08:01:07 +01:00
Eddie Hung
2105ae176a
Check for either sign or zero extension for postAdd packing
2019-11-26 22:51:00 -08:00
Eddie Hung
09637dd3e4
Fix submod -hidden
2019-11-26 11:57:26 -08:00
Eddie Hung
3027f015c2
clkpart to use 'submod -hidden'
2019-11-26 11:35:32 -08:00
Eddie Hung
e8aa92ca35
Add -hidden option to submod
2019-11-26 11:35:15 -08:00
Eddie Hung
eb666b4677
Update docs with bullet points
2019-11-26 11:12:58 -08:00
Eddie Hung
0d7ba77426
Move \init from source wire to submod if output port
2019-11-25 16:07:47 -08:00
Eddie Hung
6831510f5b
Fix debug
2019-11-25 12:59:34 -08:00
Eddie Hung
d087024caf
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-25 12:42:09 -08:00
Eddie Hung
180cb39395
abc9 to contain time call
2019-11-25 12:35:57 -08:00
Eddie Hung
f50b6422b0
abc9 to no longer to clock partitioning, operate on whole modules only
2019-11-25 12:35:38 -08:00
Eddie Hung
63b7a48fbc
clkpart to analyse async flops too
2019-11-25 12:04:11 -08:00
Marcin Kościelnicki
6cdea425b8
clkbufmap: Add support for inverters in clock path.
2019-11-25 20:40:39 +01:00
Eddie Hung
23ecf12bbf
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-23 10:29:03 -08:00
Eddie Hung
15aa3f460d
More oopsies
2019-11-23 10:28:46 -08:00
Eddie Hung
bf1167bc64
Conditioning abc9 on POs not accurate due to cells
2019-11-23 10:26:55 -08:00
Eddie Hung
7b2bccb3d3
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-23 10:18:06 -08:00
Eddie Hung
722eeacc09
Print ".en=" only if there is an enable signal
2019-11-23 10:17:31 -08:00
Eddie Hung
907c8aeaef
Escape IdStrings
2019-11-23 10:16:56 -08:00
Eddie Hung
165f5cb6cf
More sane naming of submod
2019-11-23 10:01:09 -08:00
Eddie Hung
66ff0511a0
Add -set_attr option, -unpart to take attr name
2019-11-23 09:52:17 -08:00
Eddie Hung
fb49da21bd
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-23 08:39:19 -08:00
Eddie Hung
96941aacbb
Do not use log_signal() for empty SigSpec to prevent "{ }"
2019-11-22 23:29:10 -08:00
Eddie Hung
736b96b186
Call submod once, more meaningful submod names, ignore largest domain
2019-11-22 23:16:15 -08:00
Eddie Hung
1851f4b488
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-22 23:01:18 -08:00
Eddie Hung
d223e11a72
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 22:28:35 -08:00
Eddie Hung
cba3073026
submod to bitty rather bussy, for bussy wires used as input and output
2019-11-22 20:53:58 -08:00
Eddie Hung
900c806d4e
Move clkpart into passes/hierarchy
2019-11-22 17:25:53 -08:00
Eddie Hung
2c5dfd802d
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 17:24:45 -08:00
Eddie Hung
8119383f81
Constant driven signals are also an input to submodules
2019-11-22 17:23:51 -08:00
Eddie Hung
89a4a4d90f
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 17:04:33 -08:00
Eddie Hung
573396851a
Oops
2019-11-22 17:03:30 -08:00
Eddie Hung
bf7d36627e
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-22 17:00:35 -08:00
Eddie Hung
95af8f56e4
Only action if there is more than one clock domain
2019-11-22 17:00:11 -08:00
Eddie Hung
00d76f6cc4
Replace TODO
2019-11-22 16:58:08 -08:00
Eddie Hung
0806b8e398
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 16:50:56 -08:00
Eddie Hung
6a52897aee
sigmap(wire) should inherit port_output status of POs
2019-11-22 16:48:11 -08:00
Eddie Hung
698854955c
Merge branch 'eddie/clkpart' into xaig_dff
2019-11-22 15:41:48 -08:00
Eddie Hung
84153288bb
Brackets
2019-11-22 15:41:34 -08:00
Eddie Hung
3df191cec5
Entry in Makefile.inc
2019-11-22 15:41:23 -08:00
Eddie Hung
bd56161775
Merge branch 'eddie/clkpart' into xaig_dff
2019-11-22 15:38:48 -08:00
Eddie Hung
856a3dc98d
New 'clkpart' to {,un}partition design according to clock/enable
2019-11-22 15:35:51 -08:00
Clifford Wolf
03fb92ed6f
Add "opt_mem" pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-22 17:45:22 +01:00
Eddie Hung
c4ec42ac38
When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_
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Since they should be captured downwards from the owning flop
2019-11-21 16:17:03 -08:00
David Shah
ca99b1ee8d
proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-21 20:46:41 +00:00
Eddie Hung
729c6b93e8
endomain -> ctrldomain
2019-11-20 14:32:01 -08:00
Eddie Hung
09ee96e8c2
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-19 15:40:39 -08:00
Marcin Kościelnicki
15232a48af
Fix #1462 , #1480 .
2019-11-19 08:57:39 +01:00
David Shah
7ff5d6d30a
memory_collect: Copy attr from RTLIL::Memory to cell
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-18 13:58:03 +00:00
Marcin Kościelnicki
38e72d6e13
Fix #1496 .
2019-11-18 04:16:48 +01:00
Clifford Wolf
527434de49
Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arst
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wreduce: Don't trim zeros or sext when not matching ARST_VALUE
2019-11-17 10:42:30 +01:00
David Shah
f5804a84fd
wreduce: Don't trim zeros or sext when not matching ARST_VALUE
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-14 18:43:15 +00:00
Clifford Wolf
e907ee4fde
Merge pull request #1490 from YosysHQ/clifford/autoname
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Add "autoname" pass and use it in "synth_ice40"
2019-11-14 18:03:44 +01:00
Clifford Wolf
07c854b7af
Add "autoname" pass and use it in "synth_ice40"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-13 13:41:16 +01:00
whitequark
ab0fb19cff
Merge pull request #1488 from whitequark/flowmap-fixes
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flowmap: fix a few crashes
2019-11-13 11:57:17 +00:00
Clifford Wolf
4be5a0fd7c
Update fsm_detect bugfix
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-12 17:31:30 +01:00
Clifford Wolf
16df8f5a32
Bugfix in fsm_detect
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-12 14:26:02 +01:00
whitequark
c68722818a
flowmap: when doing mincut, ensure source is always in X, not X̅.
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Fixes #1475 .
2019-11-12 00:15:43 +00:00
whitequark
eef32195bd
flowmap: don't break if that creates a k+2 (and larger) LUT either.
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Fixes #1405 .
2019-11-11 23:13:00 +00:00
Sean Cross
82f60ba938
Makefile: don't assume python is called `python3`
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On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`. The build system assumes
that python is called `python3`, which breaks under this architecture.
There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS. Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.
Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-10-19 14:04:52 +08:00
Clifford Wolf
b8774ae849
Fix dffmux peepopt init handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 11:40:32 +02:00
Clifford Wolf
bb0851bfc5
Move GENERATE_PATTERN macro to separate utility header
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 11:40:01 +02:00
Clifford Wolf
af61d92441
Disable left-over log_debug in peepopt_dffmux.pmg
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 10:43:47 +02:00
Eddie Hung
304e5f9ea4
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-08 13:03:06 -07:00
Eddie Hung
ea54b5ea61
Revert "Be mindful that sigmap(wire) could have dupes when checking \init"
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This reverts commit f46ac1df9f
.
2019-10-08 12:41:24 -07:00
Eddie Hung
cfc181cba9
Merge pull request #1432 from YosysHQ/eddie/fix1427
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Refactor peepopt_dffmux and be sensitive to \init when trimming
2019-10-08 12:38:29 -07:00
Eddie Hung
4c89a4e642
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync
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async2sync to be called by equiv_opt only when -async2sync given
2019-10-08 10:53:44 -07:00
Eddie Hung
9fd2ddb14c
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
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Rename abc_* names/attributes to more precisely be abc9_*
2019-10-08 10:53:38 -07:00
Eddie Hung
472b5d33a6
Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_comments
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Add notes and comments for xilinx_dsp
2019-10-08 10:53:30 -07:00
Eddie Hung
2cb2116b4c
Use "abc9_period" attribute for delay target
2019-10-07 15:03:44 -07:00
Clifford Wolf
4072a96663
Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarry
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Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
2019-10-06 12:11:20 +02:00
Eddie Hung
3879ca1398
Do not require changes to cells_sim.v; try and work out comb model
2019-10-05 22:55:18 -07:00
Eddie Hung
5c68da4150
Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
2019-10-05 09:27:12 -07:00
Clifford Wolf
10d0bad67e
Update README.md
2019-10-05 18:13:04 +02:00
Eddie Hung
f90a4b1e24
Missed this
2019-10-05 08:57:37 -07:00
Eddie Hung
991c2ca95b
Add comment on why we have to match for clock-enable/reset muxes
2019-10-05 08:56:37 -07:00
Eddie Hung
ebb059896a
Add note on pattern detector
2019-10-05 08:53:01 -07:00
Miodrag Milanović
7c074ef844
Merge pull request #1436 from YosysHQ/mmicko/msvc_fix
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Fixes for MSVC build
2019-10-05 07:48:30 +02:00
Eddie Hung
792cd31052
Add comments for xilinx_dsp_cascade
2019-10-04 22:31:04 -07:00
Eddie Hung
12fd2ec4f0
Improve comments for xilinx_dsp_CREG
2019-10-04 22:31:04 -07:00
Eddie Hung
14e4aeece6
Fix comment
2019-10-04 22:31:04 -07:00
Eddie Hung
8027ebf05b
Restore optimisation for sigM.empty()
2019-10-04 22:31:04 -07:00
Eddie Hung
77d7a5c14a
Retry on fixing TODOs
2019-10-04 22:31:04 -07:00
Eddie Hung
52583ecff8
Revert "Fix TODOs"
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This reverts commit 8674a6c68d563908014d16671567459499c6dc99.
2019-10-04 22:31:04 -07:00
Eddie Hung
6d68972619
More comments, cleanup
2019-10-04 22:31:04 -07:00
Eddie Hung
7de9c33931
Fix TODOs
2019-10-04 22:31:04 -07:00
Eddie Hung
983068103e
Consistency
2019-10-04 22:31:04 -07:00
Eddie Hung
cf82b38478
Add comments for xilinx_dsp
2019-10-04 22:31:04 -07:00
Eddie Hung
a5ac33f230
Merge branch 'master' into eddie/abc_to_abc9
2019-10-04 17:53:20 -07:00
Eddie Hung
f0cadb0de8
Fix from merge
2019-10-04 17:52:19 -07:00
Eddie Hung
bbc0e06af3
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-04 17:39:08 -07:00
Eddie Hung
0acc51c3d8
Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`
2019-10-04 17:35:43 -07:00
Eddie Hung
7959e9d6b2
Fix merge issues
2019-10-04 17:21:14 -07:00
Eddie Hung
7a45cd5856
Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
2019-10-04 16:58:55 -07:00
Eddie Hung
74ef8feeaf
Fix xilinx_dsp for unsigned extensions
2019-10-04 16:46:15 -07:00
Eddie Hung
aae2b9fd9c
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
Eddie Hung
84f978bdc2
Add -async2sync to help text as per @daveshah1
2019-10-04 10:17:46 -07:00
Miodrag Milanovic
c0b14cfea7
Fixes for MSVC build
2019-10-04 16:29:46 +02:00
Eddie Hung
549d6ea467
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-03 10:55:23 -07:00
Eddie Hung
a9efd2e81c
Restore part of doc
2019-10-03 10:51:53 -07:00
Eddie Hung
7a6dec1cef
Add new -async2sync option
2019-10-03 10:30:51 -07:00
Eddie Hung
8765ec3c27
Revert "equiv_opt to call async2sync when not -multiclock like SymbiYosys"
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This reverts commit a39505e329
.
2019-10-03 10:07:15 -07:00
Eddie Hung
c6d15c9aad
Revert "Update doc for equiv_opt"
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This reverts commit a274b7cc86
.
2019-10-03 10:07:03 -07:00
Clifford Wolf
0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select
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Add -select option to aigmap
2019-10-03 11:54:04 +02:00
Clifford Wolf
afdc990595
Merge pull request #1429 from YosysHQ/clifford/checkmapped
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Add "check -mapped"
2019-10-03 11:50:53 +02:00
Clifford Wolf
3e27b2846b
Add "check -allow-tbuf"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-03 11:49:56 +02:00
Eddie Hung
e9645c7fa7
Fix broken CI, check reset even for constants, trim rstmux
2019-10-02 21:26:26 -07:00
Eddie Hung
c6a55d948a
Merge branch 'eddie/fix_sat_init' into eddie/fix1427
2019-10-02 18:07:38 -07:00
Eddie Hung
d99810ad8a
Refactor peepopt_dffmux and be sensitive to \init when trimming
2019-10-02 18:01:45 -07:00
Eddie Hung
f46ac1df9f
Be mindful that sigmap(wire) could have dupes when checking \init
2019-10-02 16:08:46 -07:00
Eddie Hung
265a655ef9
Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf
2019-10-02 12:43:35 -07:00
Clifford Wolf
45e4c040d7
Add "check -mapped"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-02 13:35:03 +02:00
Eddie Hung
edc3780723
techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias
2019-09-30 17:20:12 -07:00
Eddie Hung
1b96d29174
No need to punch ports at all
2019-09-30 17:02:20 -07:00