riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #2200 from YosysHQ/mmicko/fix_expose 

expose pass fix
This commit is contained in:
Miodrag Milanović 2020-06-29 15:16:29 +02:00 committed by GitHub
parent 7860fb628f 405b4e97a1
commit 4160acc0b1
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 23 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
passes/sat/expose.cc
View File

@ -281,11 +281,15 @@ struct ExposePass : public Pass {
flag_dff = true;
continue;
}
if (args[argidx] == "-cut" && !flag_input) {
if (args[argidx] == "-cut") {
if (flag_input)
log_cmd_error("Options -cut and -input are mutually exclusive.\n");
flag_cut = true;
continue;
}
if (args[argidx] == "-input" && !flag_cut) {
if (args[argidx] == "-input") {
if (flag_cut)
log_cmd_error("Options -cut and -input are mutually exclusive.\n");
flag_input = true;
continue;
}
@ -445,6 +449,8 @@ struct ExposePass : public Pass {
SigMap out_to_in_map;
std::map<RTLIL::Wire*, RTLIL::IdString> wire_map;
for (auto w : module->wires())
{
if (flag_shared) {
@ -462,8 +468,7 @@ struct ExposePass : public Pass {
if (!w->port_input) {
w->port_input = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
RTLIL::Wire *in_wire = module->addWire(NEW_ID, GetSize(w));
out_to_in_map.add(w, in_wire);
wire_map[w] = NEW_ID;
}
}
else
@ -474,15 +479,19 @@ struct ExposePass : public Pass {
}
if (flag_cut) {
RTLIL::Wire *in_wire = add_new_wire(module, w->name.str() + sep + "i", w->width);
in_wire->port_input = true;
out_to_in_map.add(sigmap(w), in_wire);
wire_map[w] = w->name.str() + sep + "i";
}
}
}
if (flag_input)
{
for (auto &wm : wire_map)
{
RTLIL::Wire *in_wire = module->addWire(wm.second, GetSize(wm.first));
out_to_in_map.add(wm.first, in_wire);
}
for (auto cell : module->cells()) {
if (!ct.cell_known(cell->type))
continue;
@ -497,6 +506,13 @@ struct ExposePass : public Pass {
if (flag_cut)
{
for (auto &wm : wire_map)
{
RTLIL::Wire *in_wire = add_new_wire(module, wm.second, wm.first->width);
in_wire->port_input = true;
out_to_in_map.add(sigmap(wm.first), in_wire);
}
for (auto cell : module->cells()) {
if (!ct.cell_known(cell->type))
continue;