mirror of https://github.com/YosysHQ/yosys.git
More stringent check for flop cells
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83d36394f8
commit
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@ -222,7 +222,8 @@ struct OptMergeWorker
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return true;
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}
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if (cell1->type.begins_with("$") && conn1.count(ID(Q)) != 0) {
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if (conn1.count(ID(Q)) != 0 && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") || cell1->type.in("$adff", "$sr", "$ff") ||
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cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH"))) {
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std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector();
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std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector();
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for (size_t i = 0; i < q1.size(); i++)
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@ -324,7 +325,8 @@ struct OptMergeWorker
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module->connect(RTLIL::SigSig(it.second, other_sig));
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assign_map.add(it.second, other_sig);
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if (cell->type.begins_with("$") && it.first == ID(Q)) {
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if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") || cell->type.in("$adff", "$sr", "$ff") ||
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cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH"))) {
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for (auto c : it.second.chunks()) {
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auto jt = c.wire->attributes.find(ID(init));
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if (jt == c.wire->attributes.end())
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