mirror of https://github.com/YosysHQ/yosys.git
Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
This commit is contained in:
Eddie Hung
commit
7a45cd5856
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@ -215,7 +215,7 @@ struct XAigerWriter
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// box ordering, but not individual AIG cells
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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bool abc_box_seen = false;
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bool abc9_box_seen = false;
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std::vector<Cell*> flop_boxes;
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for (auto cell : module->selected_cells()) {
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@ -267,8 +267,8 @@ struct XAigerWriter
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}
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RTLIL::Module* inst_module = module->design->module(cell->type);
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if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
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abc_box_seen = true;
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if (inst_module && inst_module->attributes.count("\\abc9_box_id")) {
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abc9_box_seen = true;
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toposort.node(cell->name);
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@ -319,10 +319,10 @@ struct XAigerWriter
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if (is_output) {
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int arrival = 0;
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if (port_wire) {
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auto it = port_wire->attributes.find("\\abc_arrival");
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auto it = port_wire->attributes.find("\\abc9_arrival");
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if (it != port_wire->attributes.end()) {
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if (it->second.flags != 0)
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log_error("Attribute 'abc_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
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log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
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arrival = it->second.as_int();
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}
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}
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@ -345,7 +345,7 @@ struct XAigerWriter
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//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
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}
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if (abc_box_seen) {
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if (abc9_box_seen) {
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dict<IdString, std::pair<IdString,int>> flop_q;
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for (auto cell : flop_boxes) {
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auto r = flop_q.insert(std::make_pair(cell->type, std::make_pair(IdString(), 0)));
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@ -361,10 +361,10 @@ struct XAigerWriter
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Module *inst_module = module->design->module(cell->type);
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Wire *wire = inst_module->wire(conn.first);
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log_assert(wire);
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auto jt = wire->attributes.find("\\abc_arrival");
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auto jt = wire->attributes.find("\\abc9_arrival");
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if (jt != wire->attributes.end()) {
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if (jt->second.flags != 0)
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log_error("Attribute 'abc_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(wire), log_id(cell->type));
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log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(wire), log_id(cell->type));
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r.first->second.second = jt->second.as_int();
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}
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d = rhs;
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@ -413,7 +413,7 @@ struct XAigerWriter
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log_assert(cell);
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RTLIL::Module* box_module = module->design->module(cell->type);
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if (!box_module || !box_module->attributes.count("\\abc_box_id"))
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if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
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continue;
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bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
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@ -464,7 +464,7 @@ struct XAigerWriter
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else {
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Wire *wire = module->addWire(NEW_ID, GetSize(w));
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if (blackbox)
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wire->set_bool_attribute(ID(abc_padding));
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wire->set_bool_attribute(ID(abc9_padding));
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rhs = wire;
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cell->setPort(port_name, rhs);
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}
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@ -812,7 +812,7 @@ struct XAigerWriter
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write_h_buffer(box_inputs);
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write_h_buffer(box_outputs);
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write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int());
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write_h_buffer(box_module->attributes.at("\\abc9_box_id").as_int());
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write_h_buffer(box_count++);
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}
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@ -747,22 +747,22 @@ void AigerReader::post_process()
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flops.insert(cell->type);
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is_flop = true;
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}
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auto it = box_module->attributes.find("\\abc_carry");
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auto it = box_module->attributes.find("\\abc9_carry");
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if (it != box_module->attributes.end()) {
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RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
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auto carry_in_out = it->second.decode_string();
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auto pos = carry_in_out.find(',');
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if (pos == std::string::npos)
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log_error("'abc_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type));
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log_error("'abc9_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type));
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auto carry_in_name = RTLIL::escape_id(carry_in_out.substr(0, pos));
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carry_in = box_module->wire(carry_in_name);
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if (!carry_in || !carry_in->port_input)
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log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str());
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log_error("'abc9_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str());
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auto carry_out_name = RTLIL::escape_id(carry_in_out.substr(pos+1));
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carry_out = box_module->wire(carry_out_name);
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if (!carry_out || !carry_out->port_output)
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log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str());
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log_error("'abc9_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str());
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auto &ports = box_module->ports;
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for (auto jt = ports.begin(); jt != ports.end(); ) {
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@ -66,22 +66,21 @@ PRIVATE_NAMESPACE_BEGIN
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bool markgroups;
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int map_autoidx;
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inline std::string remap_name(RTLIL::IdString abc_name)
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inline std::string remap_name(RTLIL::IdString abc9_name)
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{
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return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1);
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return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
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}
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void handle_loops(RTLIL::Design *design, RTLIL::Module *module)
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{
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// FIXME: Do not run on all modules in design!?!
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Pass::call(design, "scc -set_attr abc_scc_id {} % w:*");
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Pass::call(design, "scc -set_attr abc9_scc_id {} % w:*");
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// For every unique SCC found, (arbitrarily) find the first
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// cell in the component, and select (and mark) all its output
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// wires
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pool<RTLIL::Const> ids_seen;
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for (auto cell : module->cells()) {
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auto it = cell->attributes.find(ID(abc_scc_id));
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auto it = cell->attributes.find(ID(abc9_scc_id));
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if (it != cell->attributes.end()) {
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auto r = ids_seen.insert(it->second);
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if (r.second) {
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@ -101,7 +100,7 @@ void handle_loops(RTLIL::Design *design, RTLIL::Module *module)
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log_assert(w->port_input);
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log_assert(b.offset < GetSize(w));
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}
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w->set_bool_attribute(ID(abc_scc_break));
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w->set_bool_attribute(ID(abc9_scc_break));
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module->swap_names(b.wire, w);
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c.second = RTLIL::SigBit(w, b.offset);
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}
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@ -114,7 +113,7 @@ void handle_loops(RTLIL::Design *design, RTLIL::Module *module)
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module->fixup_ports();
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}
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std::string add_echos_to_abc_cmd(std::string str)
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std::string add_echos_to_abc9_cmd(std::string str)
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{
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std::string new_str, token;
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for (size_t i = 0; i < str.size(); i++) {
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@ -136,7 +135,7 @@ std::string add_echos_to_abc_cmd(std::string str)
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return new_str;
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}
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std::string fold_abc_cmd(std::string str)
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std::string fold_abc9_cmd(std::string str)
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{
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std::string token, new_str = " ";
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int char_counter = 10;
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@ -180,7 +179,7 @@ std::string replace_tempdir(std::string text, std::string tempdir_name, bool sho
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return text;
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}
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struct abc_output_filter
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struct abc9_output_filter
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{
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bool got_cr;
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int escape_seq_state;
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@ -188,7 +187,7 @@ struct abc_output_filter
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std::string tempdir_name;
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bool show_tempdir;
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abc_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir)
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abc9_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir)
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{
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got_cr = false;
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escape_seq_state = 0;
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@ -255,68 +254,68 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
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log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
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module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
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std::string abc_script;
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std::string abc9_script;
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if (!lut_costs.empty()) {
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abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
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abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
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if (!box_file.empty())
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abc_script += stringf("read_box -v %s; ", box_file.c_str());
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abc9_script += stringf("read_box -v %s; ", box_file.c_str());
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}
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else
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if (!lut_file.empty()) {
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abc_script += stringf("read_lut %s; ", lut_file.c_str());
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abc9_script += stringf("read_lut %s; ", lut_file.c_str());
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if (!box_file.empty())
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abc_script += stringf("read_box -v %s; ", box_file.c_str());
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abc9_script += stringf("read_box -v %s; ", box_file.c_str());
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}
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else
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log_abort();
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abc_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
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abc9_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
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if (!script_file.empty()) {
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if (script_file[0] == '+') {
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for (size_t i = 1; i < script_file.size(); i++)
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if (script_file[i] == '\'')
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abc_script += "'\\''";
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abc9_script += "'\\''";
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else if (script_file[i] == ',')
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abc_script += " ";
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abc9_script += " ";
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else
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abc_script += script_file[i];
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abc9_script += script_file[i];
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} else
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abc_script += stringf("source %s", script_file.c_str());
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abc9_script += stringf("source %s", script_file.c_str());
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} else if (!lut_costs.empty() || !lut_file.empty()) {
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//bool all_luts_cost_same = true;
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//for (int this_cost : lut_costs)
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// if (this_cost != lut_costs.front())
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// all_luts_cost_same = false;
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abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
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abc9_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
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//if (all_luts_cost_same && !fast_mode)
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// abc_script += "; lutpack {S}";
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// abc9_script += "; lutpack {S}";
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} else
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log_abort();
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//if (script_file.empty() && !delay_target.empty())
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// for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1))
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// abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8);
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// for (size_t pos = abc9_script.find("dretime;"); pos != std::string::npos; pos = abc9_script.find("dretime;", pos+1))
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// abc9_script = abc9_script.substr(0, pos) + "dretime; retime -o {D};" + abc9_script.substr(pos+8);
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for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
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abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
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for (size_t pos = abc9_script.find("{D}"); pos != std::string::npos; pos = abc9_script.find("{D}", pos))
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abc9_script = abc9_script.substr(0, pos) + delay_target + abc9_script.substr(pos+3);
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//for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
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// abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
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//for (size_t pos = abc9_script.find("{S}"); pos != std::string::npos; pos = abc9_script.find("{S}", pos))
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// abc9_script = abc9_script.substr(0, pos) + lutin_shared + abc9_script.substr(pos+3);
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for (size_t pos = abc_script.find("{W}"); pos != std::string::npos; pos = abc_script.find("{W}", pos))
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abc_script = abc_script.substr(0, pos) + wire_delay + abc_script.substr(pos+3);
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for (size_t pos = abc9_script.find("{W}"); pos != std::string::npos; pos = abc9_script.find("{W}", pos))
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abc9_script = abc9_script.substr(0, pos) + wire_delay + abc9_script.substr(pos+3);
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abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
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abc_script = add_echos_to_abc_cmd(abc_script);
|
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abc9_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
|
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abc9_script = add_echos_to_abc9_cmd(abc9_script);
|
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|
||||
for (size_t i = 0; i+1 < abc_script.size(); i++)
|
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if (abc_script[i] == ';' && abc_script[i+1] == ' ')
|
||||
abc_script[i+1] = '\n';
|
||||
for (size_t i = 0; i+1 < abc9_script.size(); i++)
|
||||
if (abc9_script[i] == ';' && abc9_script[i+1] == ' ')
|
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abc9_script[i+1] = '\n';
|
||||
|
||||
FILE *f = fopen(stringf("%s/abc.script", tempdir_name.c_str()).c_str(), "wt");
|
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fprintf(f, "%s\n", abc_script.c_str());
|
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fprintf(f, "%s\n", abc9_script.c_str());
|
||||
fclose(f);
|
||||
|
||||
bool count_output = false;
|
||||
|
|
@ -364,7 +363,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
|
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// the expose operation -- remove them from PO/PI
|
||||
// and re-connecting them back together
|
||||
for (auto wire : module->wires()) {
|
||||
auto it = wire->attributes.find(ID(abc_scc_break));
|
||||
auto it = wire->attributes.find(ID(abc9_scc_break));
|
||||
if (it != wire->attributes.end()) {
|
||||
wire->attributes.erase(it);
|
||||
log_assert(wire->port_output);
|
||||
|
|
@ -394,22 +393,22 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
|
|||
log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
|
||||
|
||||
#ifndef YOSYS_LINK_ABC
|
||||
abc_output_filter filt(tempdir_name, show_tempdir);
|
||||
int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
|
||||
abc9_output_filter filt(tempdir_name, show_tempdir);
|
||||
int ret = run_command(buffer, std::bind(&abc9_output_filter::next_line, filt, std::placeholders::_1));
|
||||
#else
|
||||
// These needs to be mutable, supposedly due to getopt
|
||||
char *abc_argv[5];
|
||||
char *abc9_argv[5];
|
||||
string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str());
|
||||
abc_argv[0] = strdup(exe_file.c_str());
|
||||
abc_argv[1] = strdup("-s");
|
||||
abc_argv[2] = strdup("-f");
|
||||
abc_argv[3] = strdup(tmp_script_name.c_str());
|
||||
abc_argv[4] = 0;
|
||||
int ret = Abc_RealMain(4, abc_argv);
|
||||
free(abc_argv[0]);
|
||||
free(abc_argv[1]);
|
||||
free(abc_argv[2]);
|
||||
free(abc_argv[3]);
|
||||
abc9_argv[0] = strdup(exe_file.c_str());
|
||||
abc9_argv[1] = strdup("-s");
|
||||
abc9_argv[2] = strdup("-f");
|
||||
abc9_argv[3] = strdup(tmp_script_name.c_str());
|
||||
abc9_argv[4] = 0;
|
||||
int ret = Abc_RealMain(4, abc9_argv);
|
||||
free(abc9_argv[0]);
|
||||
free(abc9_argv[1]);
|
||||
free(abc9_argv[2]);
|
||||
free(abc9_argv[3]);
|
||||
#endif
|
||||
if (ret != 0)
|
||||
log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
|
||||
|
|
@ -457,17 +456,17 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
|
|||
signal = std::move(bits);
|
||||
}
|
||||
|
||||
dict<IdString, bool> abc_box;
|
||||
dict<IdString, bool> abc9_box;
|
||||
vector<RTLIL::Cell*> boxes;
|
||||
for (auto cell : module->selected_cells()) {
|
||||
if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC_FF_))) {
|
||||
module->remove(cell);
|
||||
continue;
|
||||
}
|
||||
auto jt = abc_box.find(cell->type);
|
||||
if (jt == abc_box.end()) {
|
||||
auto jt = abc9_box.find(cell->type);
|
||||
if (jt == abc9_box.end()) {
|
||||
RTLIL::Module* box_module = design->module(cell->type);
|
||||
jt = abc_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc_box_id)))).first;
|
||||
jt = abc9_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc9_box_id)))).first;
|
||||
}
|
||||
if (jt->second)
|
||||
boxes.emplace_back(cell);
|
||||
|
|
@ -564,7 +563,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
|
|||
}
|
||||
|
||||
RTLIL::Module* box_module = design->module(mapped_cell->type);
|
||||
auto abc_flop = box_module && box_module->attributes.count("\\abc9_flop");
|
||||
auto abc9_flop = box_module && box_module->attributes.count("\\abc9_flop");
|
||||
for (auto &conn : mapped_cell->connections()) {
|
||||
RTLIL::SigSpec newsig;
|
||||
for (auto c : conn.second.chunks()) {
|
||||
|
|
@ -577,7 +576,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
|
|||
}
|
||||
cell->setPort(conn.first, newsig);
|
||||
|
||||
if (!abc_flop) {
|
||||
if (!abc9_flop) {
|
||||
if (cell->input(conn.first)) {
|
||||
for (auto i : newsig)
|
||||
bit2sinks[i].push_back(cell);
|
||||
|
|
@ -598,7 +597,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
|
|||
if (!conn.second.is_wire())
|
||||
continue;
|
||||
Wire *wire = conn.second.as_wire();
|
||||
if (!wire->get_bool_attribute(ID(abc_padding)))
|
||||
if (!wire->get_bool_attribute(ID(abc9_padding)))
|
||||
continue;
|
||||
cell->unsetPort(conn.first);
|
||||
log_debug("Dropping padded port connection for %s (%s) .%s (%s )\n", log_id(cell), cell->type.c_str(), log_id(conn.first), log_signal(conn.second));
|
||||
|
|
@ -777,17 +776,17 @@ struct Abc9Pass : public Pass {
|
|||
log(" if no -script parameter is given, the following scripts are used:\n");
|
||||
log("\n");
|
||||
log(" for -lut/-luts (only one LUT size):\n");
|
||||
log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT /*"; lutpack {S}"*/).c_str());
|
||||
log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT /*"; lutpack {S}"*/).c_str());
|
||||
log("\n");
|
||||
log(" for -lut/-luts (different LUT sizes):\n");
|
||||
log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str());
|
||||
log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT).c_str());
|
||||
log("\n");
|
||||
log(" -fast\n");
|
||||
log(" use different default scripts that are slightly faster (at the cost\n");
|
||||
log(" of output quality):\n");
|
||||
log("\n");
|
||||
log(" for -lut/-luts:\n");
|
||||
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str());
|
||||
log("%s\n", fold_abc9_cmd(ABC_FAST_COMMAND_LUT).c_str());
|
||||
log("\n");
|
||||
log(" -D <picoseconds>\n");
|
||||
log(" set delay target. the string {D} in the default scripts above is\n");
|
||||
|
|
@ -1005,7 +1004,7 @@ struct Abc9Pass : public Pass {
|
|||
|
||||
dict<int,IdString> box_lookup;
|
||||
for (auto m : design->modules()) {
|
||||
auto it = m->attributes.find(ID(abc_box_id));
|
||||
auto it = m->attributes.find(ID(abc9_box_id));
|
||||
if (it == m->attributes.end())
|
||||
continue;
|
||||
if (m->name.begins_with("$paramod"))
|
||||
|
|
@ -1013,7 +1012,7 @@ struct Abc9Pass : public Pass {
|
|||
auto id = it->second.as_int();
|
||||
auto r = box_lookup.insert(std::make_pair(id, m->name));
|
||||
if (!r.second)
|
||||
log_error("Module '%s' has the same abc_box_id = %d value as '%s'.\n",
|
||||
log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
|
||||
log_id(m), id, log_id(r.first->second));
|
||||
log_assert(r.second);
|
||||
|
||||
|
|
@ -1021,24 +1020,24 @@ struct Abc9Pass : public Pass {
|
|||
for (auto p : m->ports) {
|
||||
auto w = m->wire(p);
|
||||
log_assert(w);
|
||||
if (w->attributes.count(ID(abc_carry))) {
|
||||
if (w->attributes.count(ID(abc9_carry))) {
|
||||
if (w->port_input) {
|
||||
if (carry_in)
|
||||
log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m));
|
||||
log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
|
||||
carry_in = w;
|
||||
}
|
||||
else if (w->port_output) {
|
||||
if (carry_out)
|
||||
log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m));
|
||||
log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
|
||||
carry_out = w;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (carry_in || carry_out) {
|
||||
if (carry_in && !carry_out)
|
||||
log_error("Module '%s' contains an 'abc_carry' input port but no output port.\n", log_id(m));
|
||||
log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
|
||||
if (!carry_in && carry_out)
|
||||
log_error("Module '%s' contains an 'abc_carry' output port but no input port.\n", log_id(m));
|
||||
log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
|
||||
// Make carry_in the last PI, and carry_out the last PO
|
||||
// since ABC requires it this way
|
||||
auto &ports = m->ports;
|
||||
|
|
@ -1066,7 +1065,7 @@ struct Abc9Pass : public Pass {
|
|||
|
||||
for (auto module : design->selected_modules())
|
||||
{
|
||||
if (module->attributes.count(ID(abc_box_id)))
|
||||
if (module->attributes.count(ID(abc9_box_id)))
|
||||
continue;
|
||||
|
||||
if (module->processes.size() > 0) {
|
||||
|
|
|
|||
|
|
@ -15,12 +15,12 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
|
|||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
|
||||
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_map.v))
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_unmap.v))
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_model.v))
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut))
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_map.v))
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_unmap.v))
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_model.v))
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.box))
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.lut))
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g_nowide.lut))
|
||||
|
||||
EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
|
||||
.SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ CCU2C 1 1 9 3
|
|||
# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
|
||||
# Outputs: DO0, DO1, DO2, DO3
|
||||
# name ID w/b ins outs
|
||||
$__ABC_DPR16X4_COMB 2 0 8 4
|
||||
$__ABC9_DPR16X4_COMB 2 0 8 4
|
||||
|
||||
#A0 A1 A2 A3 RAD0 RAD1 RAD2 RAD3
|
||||
0 0 0 0 141 379 275 379
|
||||
|
|
@ -20,5 +20,5 @@ module TRELLIS_DPR16X4 (
|
|||
.RAD(RAD), .DO(\$DO )
|
||||
);
|
||||
|
||||
\$__ABC_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO));
|
||||
\$__ABC9_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO));
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
// ---------------------------------------
|
||||
|
||||
(* abc9_box_id=2 *)
|
||||
module \$__ABC9_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
|
||||
endmodule
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
// ---------------------------------------
|
||||
|
||||
module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
|
||||
module \$__ABC9_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
|
||||
assign Y = A;
|
||||
endmodule
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
// ---------------------------------------
|
||||
|
||||
(* abc_box_id=2 *)
|
||||
module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
|
||||
endmodule
|
||||
|
|
@ -9,19 +9,19 @@ module LUT4(input A, B, C, D, output Z);
|
|||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
(* abc_box_id=4, lib_whitebox *)
|
||||
(* abc9_box_id=4, lib_whitebox *)
|
||||
module L6MUX21 (input D0, D1, SD, output Z);
|
||||
assign Z = SD ? D1 : D0;
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
(* abc_box_id=1, lib_whitebox *)
|
||||
(* abc9_box_id=1, lib_whitebox *)
|
||||
module CCU2C(
|
||||
(* abc_carry *)
|
||||
(* abc9_carry *)
|
||||
input CIN,
|
||||
input A0, B0, C0, D0, A1, B1, C1, D1,
|
||||
output S0, S1,
|
||||
(* abc_carry *)
|
||||
(* abc9_carry *)
|
||||
output COUT
|
||||
);
|
||||
parameter [15:0] INIT0 = 16'h0000;
|
||||
|
|
@ -103,7 +103,7 @@ module TRELLIS_RAM16X2 (
|
|||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
(* abc_box_id=3, lib_whitebox *)
|
||||
(* abc9_box_id=3, lib_whitebox *)
|
||||
module PFUMX (input ALUT, BLUT, C0, output Z);
|
||||
assign Z = C0 ? ALUT : BLUT;
|
||||
endmodule
|
||||
|
|
@ -115,7 +115,7 @@ module TRELLIS_DPR16X4 (
|
|||
input WRE,
|
||||
input WCK,
|
||||
input [3:0] RAD,
|
||||
/* (* abc_arrival=<TODO> *) */
|
||||
/* (* abc9_arrival=<TODO> *) */
|
||||
output [3:0] DO
|
||||
);
|
||||
parameter WCKMUX = "WCK";
|
||||
|
|
|
|||
|
|
@ -307,15 +307,16 @@ struct SynthEcp5Pass : public ScriptPass
|
|||
}
|
||||
std::string techmap_args = "-map +/ecp5/latches_map.v";
|
||||
if (abc9)
|
||||
techmap_args += " -map +/ecp5/abc_map.v -max_iter 1";
|
||||
techmap_args += " -map +/ecp5/abc9_map.v -max_iter 1";
|
||||
run("techmap " + techmap_args);
|
||||
|
||||
if (abc9) {
|
||||
run("read_verilog -icells -lib +/ecp5/abc9_model.v");
|
||||
if (nowidelut)
|
||||
run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
|
||||
run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200");
|
||||
else
|
||||
run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
|
||||
run("techmap -map +/ecp5/abc_unmap.v");
|
||||
run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200");
|
||||
run("techmap -map +/ecp5/abc9_unmap.v");
|
||||
} else {
|
||||
if (nowidelut)
|
||||
run("abc -lut 4 -dress");
|
||||
|
|
|
|||
|
|
@ -28,12 +28,13 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
|
|||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.lut))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_u.box))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_u.lut))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_model.v))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_hx.box))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_hx.lut))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_lp.box))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_lp.lut))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_u.box))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_u.lut))
|
||||
|
||||
$(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
|
||||
$(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
|
||||
|
|
|
|||
|
|
@ -0,0 +1,27 @@
|
|||
(* abc9_box_id = 1, lib_whitebox *)
|
||||
module \$__ICE40_CARRY_WRAPPER (
|
||||
(* abc9_carry *)
|
||||
output CO,
|
||||
output O,
|
||||
input A, B,
|
||||
(* abc9_carry *)
|
||||
input CI,
|
||||
input I0, I3
|
||||
);
|
||||
parameter LUT = 0;
|
||||
SB_CARRY carry (
|
||||
.I0(A),
|
||||
.I1(B),
|
||||
.CI(CI),
|
||||
.CO(CO)
|
||||
);
|
||||
SB_LUT4 #(
|
||||
.LUT_INIT(LUT)
|
||||
) adder (
|
||||
.I0(I0),
|
||||
.I1(A),
|
||||
.I2(B),
|
||||
.I3(I3),
|
||||
.O(O)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -2,9 +2,9 @@
|
|||
`define SB_DFF_REG reg Q = 0
|
||||
// `define SB_DFF_REG reg Q
|
||||
|
||||
`define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
|
||||
`define ABC_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc_arrival=TIME *) `endif
|
||||
`define ABC_ARRIVAL_U(TIME) `ifdef ICE40_U (* abc_arrival=TIME *) `endif
|
||||
`define ABC9_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc9_arrival=TIME *) `endif
|
||||
`define ABC9_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc9_arrival=TIME *) `endif
|
||||
`define ABC9_ARRIVAL_U(TIME) `ifdef ICE40_U (* abc9_arrival=TIME *) `endif
|
||||
|
||||
// SiliconBlue IO Cells
|
||||
|
||||
|
|
@ -145,34 +145,6 @@ module SB_CARRY (output CO, input I0, I1, CI);
|
|||
assign CO = (I0 && I1) || ((I0 || I1) && CI);
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 1, lib_whitebox *)
|
||||
module \$__ICE40_CARRY_WRAPPER (
|
||||
(* abc_carry *)
|
||||
output CO,
|
||||
output O,
|
||||
input A, B,
|
||||
(* abc_carry *)
|
||||
input CI,
|
||||
input I0, I3
|
||||
);
|
||||
parameter LUT = 0;
|
||||
SB_CARRY carry (
|
||||
.I0(A),
|
||||
.I1(B),
|
||||
.CI(CI),
|
||||
.CO(CO)
|
||||
);
|
||||
SB_LUT4 #(
|
||||
.LUT_INIT(LUT)
|
||||
) adder (
|
||||
.I0(I0),
|
||||
.I1(A),
|
||||
.I2(B),
|
||||
.I3(I3),
|
||||
.O(O)
|
||||
);
|
||||
endmodule
|
||||
|
||||
// Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
|
||||
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
|
||||
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
|
||||
|
|
@ -180,9 +152,9 @@ endmodule
|
|||
// Positive Edge SiliconBlue FF Cells
|
||||
|
||||
module SB_DFF (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, D
|
||||
);
|
||||
|
|
@ -191,9 +163,9 @@ module SB_DFF (
|
|||
endmodule
|
||||
|
||||
module SB_DFFE (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, E, D
|
||||
);
|
||||
|
|
@ -203,9 +175,9 @@ module SB_DFFE (
|
|||
endmodule
|
||||
|
||||
module SB_DFFSR (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, R, D
|
||||
);
|
||||
|
|
@ -217,9 +189,9 @@ module SB_DFFSR (
|
|||
endmodule
|
||||
|
||||
module SB_DFFR (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, R, D
|
||||
);
|
||||
|
|
@ -231,9 +203,9 @@ module SB_DFFR (
|
|||
endmodule
|
||||
|
||||
module SB_DFFSS (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, S, D
|
||||
);
|
||||
|
|
@ -245,9 +217,9 @@ module SB_DFFSS (
|
|||
endmodule
|
||||
|
||||
module SB_DFFS (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, S, D
|
||||
);
|
||||
|
|
@ -259,9 +231,9 @@ module SB_DFFS (
|
|||
endmodule
|
||||
|
||||
module SB_DFFESR (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, E, R, D
|
||||
);
|
||||
|
|
@ -275,9 +247,9 @@ module SB_DFFESR (
|
|||
endmodule
|
||||
|
||||
module SB_DFFER (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, E, R, D
|
||||
);
|
||||
|
|
@ -289,9 +261,9 @@ module SB_DFFER (
|
|||
endmodule
|
||||
|
||||
module SB_DFFESS (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, E, S, D
|
||||
);
|
||||
|
|
@ -305,9 +277,9 @@ module SB_DFFESS (
|
|||
endmodule
|
||||
|
||||
module SB_DFFES (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, E, S, D
|
||||
);
|
||||
|
|
@ -321,9 +293,9 @@ endmodule
|
|||
// Negative Edge SiliconBlue FF Cells
|
||||
|
||||
module SB_DFFN (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, D
|
||||
);
|
||||
|
|
@ -332,9 +304,9 @@ module SB_DFFN (
|
|||
endmodule
|
||||
|
||||
module SB_DFFNE (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, E, D
|
||||
);
|
||||
|
|
@ -344,9 +316,9 @@ module SB_DFFNE (
|
|||
endmodule
|
||||
|
||||
module SB_DFFNSR (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, R, D
|
||||
);
|
||||
|
|
@ -358,9 +330,9 @@ module SB_DFFNSR (
|
|||
endmodule
|
||||
|
||||
module SB_DFFNR (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, R, D
|
||||
);
|
||||
|
|
@ -372,9 +344,9 @@ module SB_DFFNR (
|
|||
endmodule
|
||||
|
||||
module SB_DFFNSS (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, S, D
|
||||
);
|
||||
|
|
@ -386,9 +358,9 @@ module SB_DFFNSS (
|
|||
endmodule
|
||||
|
||||
module SB_DFFNS (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, S, D
|
||||
);
|
||||
|
|
@ -400,9 +372,9 @@ module SB_DFFNS (
|
|||
endmodule
|
||||
|
||||
module SB_DFFNESR (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, E, R, D
|
||||
);
|
||||
|
|
@ -416,9 +388,9 @@ module SB_DFFNESR (
|
|||
endmodule
|
||||
|
||||
module SB_DFFNER (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, E, R, D
|
||||
);
|
||||
|
|
@ -430,9 +402,9 @@ module SB_DFFNER (
|
|||
endmodule
|
||||
|
||||
module SB_DFFNESS (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, E, S, D
|
||||
);
|
||||
|
|
@ -446,9 +418,9 @@ module SB_DFFNESS (
|
|||
endmodule
|
||||
|
||||
module SB_DFFNES (
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output `SB_DFF_REG,
|
||||
input C, E, S, D
|
||||
);
|
||||
|
|
@ -462,9 +434,9 @@ endmodule
|
|||
// SiliconBlue RAM Cells
|
||||
|
||||
module SB_RAM40_4K (
|
||||
`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
|
||||
`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
|
||||
`ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
|
||||
`ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
|
||||
`ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
|
||||
`ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
|
||||
output [15:0] RDATA,
|
||||
input RCLK, RCLKE, RE,
|
||||
input [10:0] RADDR,
|
||||
|
|
@ -633,9 +605,9 @@ module SB_RAM40_4K (
|
|||
endmodule
|
||||
|
||||
module SB_RAM40_4KNR (
|
||||
`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
|
||||
`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
|
||||
`ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
|
||||
`ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
|
||||
`ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
|
||||
`ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
|
||||
output [15:0] RDATA,
|
||||
input RCLKN, RCLKE, RE,
|
||||
input [10:0] RADDR,
|
||||
|
|
@ -701,9 +673,9 @@ module SB_RAM40_4KNR (
|
|||
endmodule
|
||||
|
||||
module SB_RAM40_4KNW (
|
||||
`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
|
||||
`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
|
||||
`ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
|
||||
`ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
|
||||
`ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
|
||||
`ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
|
||||
output [15:0] RDATA,
|
||||
input RCLK, RCLKE, RE,
|
||||
input [10:0] RADDR,
|
||||
|
|
@ -769,9 +741,9 @@ module SB_RAM40_4KNW (
|
|||
endmodule
|
||||
|
||||
module SB_RAM40_4KNRNW (
|
||||
`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
|
||||
`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
|
||||
`ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
|
||||
`ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
|
||||
`ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
|
||||
`ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
|
||||
output [15:0] RDATA,
|
||||
input RCLKN, RCLKE, RE,
|
||||
input [10:0] RADDR,
|
||||
|
|
@ -841,9 +813,9 @@ endmodule
|
|||
module ICESTORM_LC (
|
||||
input I0, I1, I2, I3, CIN, CLK, CEN, SR,
|
||||
output LO,
|
||||
`ABC_ARRIVAL_HX(540)
|
||||
`ABC_ARRIVAL_LP(796)
|
||||
`ABC_ARRIVAL_U(1391)
|
||||
`ABC9_ARRIVAL_HX(540)
|
||||
`ABC9_ARRIVAL_LP(796)
|
||||
`ABC9_ARRIVAL_U(1391)
|
||||
output O,
|
||||
output COUT
|
||||
);
|
||||
|
|
@ -1445,7 +1417,6 @@ module SB_MAC16 (
|
|||
input ADDSUBTOP, ADDSUBBOT,
|
||||
input OHOLDTOP, OHOLDBOT,
|
||||
input CI, ACCUMCI, SIGNEXTIN,
|
||||
//`ABC_ARRIVAL_U(1984) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
|
||||
output [31:0] O,
|
||||
output CO, ACCUMCO, SIGNEXTOUT
|
||||
);
|
||||
|
|
|
|||
|
|
@ -245,7 +245,7 @@ struct SynthIce40Pass : public ScriptPass
|
|||
define = "-D ICE40_U";
|
||||
else
|
||||
define = "-D ICE40_HX";
|
||||
run("read_verilog -icells " + define + " -lib +/ice40/cells_sim.v");
|
||||
run("read_verilog " + define + " -lib +/ice40/cells_sim.v");
|
||||
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
|
||||
run("proc");
|
||||
}
|
||||
|
|
@ -349,6 +349,7 @@ struct SynthIce40Pass : public ScriptPass
|
|||
}
|
||||
if (!noabc) {
|
||||
if (abc == "abc9") {
|
||||
run("read_verilog -icells -lib +/ice40/abc9_model.v");
|
||||
int wire_delay;
|
||||
if (device_opt == "lp")
|
||||
wire_delay = 400;
|
||||
|
|
@ -356,7 +357,7 @@ struct SynthIce40Pass : public ScriptPass
|
|||
wire_delay = 750;
|
||||
else
|
||||
wire_delay = 250;
|
||||
run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
|
||||
run(abc + stringf(" -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
|
||||
}
|
||||
else
|
||||
run(abc + " -dress -lut 4", "(skip if -noabc)");
|
||||
|
|
|
|||
|
|
@ -44,12 +44,12 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
|
|||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/dsp_map.v))
|
||||
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_unmap.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_model.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7_nowide.lut))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_unmap.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_model.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_xc7.box))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_xc7.lut))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_xc7_nowide.lut))
|
||||
|
||||
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
|
||||
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
|
||||
|
|
|
|||
|
|
@ -174,8 +174,8 @@ module RAM32X1D (
|
|||
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
|
||||
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
|
||||
);
|
||||
\$__ABC_LUT6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
|
||||
\$__ABC_LUT6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
|
||||
\$__ABC9_LUT6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
|
||||
\$__ABC9_LUT6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
|
||||
endmodule
|
||||
|
||||
module RAM64X1D (
|
||||
|
|
@ -197,8 +197,8 @@ module RAM64X1D (
|
|||
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
|
||||
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
|
||||
);
|
||||
\$__ABC_LUT6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
|
||||
\$__ABC_LUT6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
|
||||
\$__ABC9_LUT6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
|
||||
\$__ABC9_LUT6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
|
||||
endmodule
|
||||
|
||||
module RAM128X1D (
|
||||
|
|
@ -219,8 +219,8 @@ module RAM128X1D (
|
|||
.A(A),
|
||||
.DPRA(DPRA)
|
||||
);
|
||||
\$__ABC_LUT7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
|
||||
\$__ABC_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO));
|
||||
\$__ABC9_LUT7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
|
||||
\$__ABC9_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO));
|
||||
endmodule
|
||||
|
||||
module SRL16E (
|
||||
|
|
@ -236,7 +236,7 @@ module SRL16E (
|
|||
.Q(\$Q ),
|
||||
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
|
||||
);
|
||||
\$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A0, A1, A2, A3, 1'b1}), .Y(Q));
|
||||
\$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A0, A1, A2, A3, 1'b1}), .Y(Q));
|
||||
endmodule
|
||||
|
||||
module SRLC32E (
|
||||
|
|
@ -254,7 +254,7 @@ module SRLC32E (
|
|||
.Q(\$Q ), .Q31(Q31),
|
||||
.A(A), .CE(CE), .CLK(CLK), .D(D)
|
||||
);
|
||||
\$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q));
|
||||
\$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q));
|
||||
endmodule
|
||||
|
||||
module DSP48E1 (
|
||||
|
|
@ -443,15 +443,15 @@ __CELL__ #(
|
|||
if (AREG == 0 && MREG == 0 && PREG == 0)
|
||||
assign iA = A, pA = 1'bx;
|
||||
else
|
||||
\$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
|
||||
\$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
|
||||
if (BREG == 0 && MREG == 0 && PREG == 0)
|
||||
assign iB = B, pB = 1'bx;
|
||||
else
|
||||
\$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
|
||||
\$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
|
||||
if (CREG == 0 && PREG == 0)
|
||||
assign iC = C, pC = 1'bx;
|
||||
else
|
||||
\$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
|
||||
\$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
|
||||
if (DREG == 0)
|
||||
assign iD = D;
|
||||
else if (techmap_guard)
|
||||
|
|
@ -462,27 +462,27 @@ __CELL__ #(
|
|||
assign pAD = 1'bx;
|
||||
if (PREG == 0) begin
|
||||
if (MREG == 1)
|
||||
\$__ABC_REG rM (.Q(pM));
|
||||
\$__ABC9_REG rM (.Q(pM));
|
||||
else
|
||||
assign pM = 1'bx;
|
||||
assign pP = 1'bx;
|
||||
end else begin
|
||||
assign pM = 1'bx;
|
||||
\$__ABC_REG rP (.Q(pP));
|
||||
\$__ABC9_REG rP (.Q(pP));
|
||||
end
|
||||
|
||||
if (MREG == 0 && PREG == 0)
|
||||
assign mP = oP, mPCOUT = oPCOUT;
|
||||
else
|
||||
assign mP = 1'bx, mPCOUT = 1'bx;
|
||||
\$__ABC_DSP48E1_MULT_P_MUX muxP (
|
||||
\$__ABC9_DSP48E1_MULT_P_MUX muxP (
|
||||
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
|
||||
);
|
||||
\$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
|
||||
\$__ABC9_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
|
||||
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
|
||||
);
|
||||
|
||||
`DSP48E1_INST(\$__ABC_DSP48E1_MULT )
|
||||
`DSP48E1_INST(\$__ABC9_DSP48E1_MULT )
|
||||
end
|
||||
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
|
||||
// Disconnect the A-input if MREG is enabled, since
|
||||
|
|
@ -490,26 +490,26 @@ __CELL__ #(
|
|||
if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0)
|
||||
assign iA = A, pA = 1'bx;
|
||||
else
|
||||
\$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
|
||||
\$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
|
||||
if (BREG == 0 && MREG == 0 && PREG == 0)
|
||||
assign iB = B, pB = 1'bx;
|
||||
else
|
||||
\$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
|
||||
\$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
|
||||
if (CREG == 0 && PREG == 0)
|
||||
assign iC = C, pC = 1'bx;
|
||||
else
|
||||
\$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
|
||||
\$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
|
||||
if (DREG == 0 && ADREG == 0)
|
||||
assign iD = D, pD = 1'bx;
|
||||
else
|
||||
\$__ABC_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD));
|
||||
\$__ABC9_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD));
|
||||
if (PREG == 0) begin
|
||||
if (MREG == 1) begin
|
||||
assign pAD = 1'bx;
|
||||
\$__ABC_REG rM (.Q(pM));
|
||||
\$__ABC9_REG rM (.Q(pM));
|
||||
end else begin
|
||||
if (ADREG == 1)
|
||||
\$__ABC_REG rAD (.Q(pAD));
|
||||
\$__ABC9_REG rAD (.Q(pAD));
|
||||
else
|
||||
assign pAD = 1'bx;
|
||||
assign pM = 1'bx;
|
||||
|
|
@ -517,21 +517,21 @@ __CELL__ #(
|
|||
assign pP = 1'bx;
|
||||
end else begin
|
||||
assign pAD = 1'bx, pM = 1'bx;
|
||||
\$__ABC_REG rP (.Q(pP));
|
||||
\$__ABC9_REG rP (.Q(pP));
|
||||
end
|
||||
|
||||
if (MREG == 0 && PREG == 0)
|
||||
assign mP = oP, mPCOUT = oPCOUT;
|
||||
else
|
||||
assign mP = 1'bx, mPCOUT = 1'bx;
|
||||
\$__ABC_DSP48E1_MULT_DPORT_P_MUX muxP (
|
||||
\$__ABC9_DSP48E1_MULT_DPORT_P_MUX muxP (
|
||||
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
|
||||
);
|
||||
\$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT (
|
||||
\$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT (
|
||||
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
|
||||
);
|
||||
|
||||
`DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT )
|
||||
`DSP48E1_INST(\$__ABC9_DSP48E1_MULT_DPORT )
|
||||
end
|
||||
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
|
||||
// Disconnect the A-input if MREG is enabled, since
|
||||
|
|
@ -539,15 +539,15 @@ __CELL__ #(
|
|||
if (AREG == 0 && PREG == 0)
|
||||
assign iA = A, pA = 1'bx;
|
||||
else
|
||||
\$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
|
||||
\$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
|
||||
if (BREG == 0 && PREG == 0)
|
||||
assign iB = B, pB = 1'bx;
|
||||
else
|
||||
\$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
|
||||
\$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
|
||||
if (CREG == 0 && PREG == 0)
|
||||
assign iC = C, pC = 1'bx;
|
||||
else
|
||||
\$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
|
||||
\$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
|
||||
if (DREG == 1 && techmap_guard)
|
||||
$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
|
||||
assign pD = 1'bx;
|
||||
|
|
@ -558,7 +558,7 @@ __CELL__ #(
|
|||
$error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
|
||||
assign pM = 1'bx;
|
||||
if (PREG == 1)
|
||||
\$__ABC_REG rP (.Q(pP));
|
||||
\$__ABC9_REG rP (.Q(pP));
|
||||
else
|
||||
assign pP = 1'bx;
|
||||
|
||||
|
|
@ -566,14 +566,14 @@ __CELL__ #(
|
|||
assign mP = oP, mPCOUT = oPCOUT;
|
||||
else
|
||||
assign mP = 1'bx, mPCOUT = 1'bx;
|
||||
\$__ABC_DSP48E1_P_MUX muxP (
|
||||
\$__ABC9_DSP48E1_P_MUX muxP (
|
||||
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
|
||||
);
|
||||
\$__ABC_DSP48E1_PCOUT_MUX muxPCOUT (
|
||||
\$__ABC9_DSP48E1_PCOUT_MUX muxPCOUT (
|
||||
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
|
||||
);
|
||||
|
||||
`DSP48E1_INST(\$__ABC_DSP48E1 )
|
||||
`DSP48E1_INST(\$__ABC9_DSP48E1 )
|
||||
end
|
||||
else
|
||||
$error("Invalid DSP48E1 configuration");
|
||||
|
|
@ -24,7 +24,7 @@
|
|||
// Necessary to make these an atomic unit so that
|
||||
// ABC cannot optimise just one of the MUXF7 away
|
||||
// and expect to save on its delay
|
||||
(* abc_box_id = 3, lib_whitebox *)
|
||||
(* abc9_box_id = 3, lib_whitebox *)
|
||||
module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
|
||||
assign O = S1 ? (S0 ? I3 : I2)
|
||||
: (S0 ? I1 : I0);
|
||||
|
|
@ -43,32 +43,32 @@ endmodule
|
|||
// is only committed on the next clock edge).
|
||||
// To model the combinatorial path, such cells have to be split
|
||||
// into comb and seq parts, with this box modelling only the former.
|
||||
(* abc_box_id=2000 *)
|
||||
module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
|
||||
(* abc9_box_id=2000 *)
|
||||
module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
|
||||
endmodule
|
||||
// Box to emulate comb/seq behaviour of RAMD128
|
||||
(* abc_box_id=2001 *)
|
||||
module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
|
||||
(* abc9_box_id=2001 *)
|
||||
module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
|
||||
endmodule
|
||||
|
||||
|
||||
// Modules used to model the comb/seq behaviour of DSP48E1
|
||||
// With abc_map.v responsible for splicing the below modules
|
||||
// With abc9_map.v responsible for splicing the below modules
|
||||
// between the combinatorial DSP48E1 box (e.g. disconnecting
|
||||
// A when AREG, MREG or PREG is enabled and splicing in the
|
||||
// "$__ABC_DSP48E1_REG" blackbox as "REG" in the diagram below)
|
||||
// "$__ABC9_DSP48E1_REG" blackbox as "REG" in the diagram below)
|
||||
// this acts to first disables the combinatorial path (as there
|
||||
// is no connectivity through REG), and secondly, since this is
|
||||
// blackbox a new PI will be introduced with an arrival time of
|
||||
// zero.
|
||||
// Note: Since these "$__ABC_DSP48E1_REG" modules are of a
|
||||
// Note: Since these "$__ABC9_DSP48E1_REG" modules are of a
|
||||
// sequential nature, they are not passed as a box to ABC and
|
||||
// (desirably) represented as PO/PIs.
|
||||
//
|
||||
// At the DSP output, we place a blackbox mux ("M" in the diagram
|
||||
// below) to capture the fact that the critical-path could come
|
||||
// from any one of its inputs.
|
||||
// In contrast to "REG", the "$__ABC_DSP48E1_*_MUX" modules are
|
||||
// In contrast to "REG", the "$__ABC9_DSP48E1_*_MUX" modules are
|
||||
// combinatorial blackboxes that do get passed to ABC.
|
||||
// The propagation delay through this box (specified in the box
|
||||
// file) captures the arrival time of the register (i.e.
|
||||
|
|
@ -97,18 +97,18 @@ endmodule
|
|||
// B >>------| |
|
||||
// +---------+
|
||||
//
|
||||
`define ABC_DSP48E1_MUX(__NAME__) """
|
||||
`define ABC9_DSP48E1_MUX(__NAME__) """
|
||||
module __NAME__ (input Aq, ADq, Bq, Cq, Dq, input [47:0] I, input Mq, input [47:0] P, input Pq, output [47:0] O);
|
||||
endmodule
|
||||
"""
|
||||
(* abc_box_id=2100 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_P_MUX )
|
||||
(* abc_box_id=2101 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_PCOUT_MUX )
|
||||
(* abc_box_id=2102 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_P_MUX )
|
||||
(* abc_box_id=2103 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX )
|
||||
(* abc_box_id=2104 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_P_MUX )
|
||||
(* abc_box_id=2105 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_PCOUT_MUX )
|
||||
(* abc9_box_id=2100 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_P_MUX )
|
||||
(* abc9_box_id=2101 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_PCOUT_MUX )
|
||||
(* abc9_box_id=2102 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_DPORT_P_MUX )
|
||||
(* abc9_box_id=2103 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX )
|
||||
(* abc9_box_id=2104 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_P_MUX )
|
||||
(* abc9_box_id=2105 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_PCOUT_MUX )
|
||||
|
||||
`define ABC_DSP48E1(__NAME__) """
|
||||
`define ABC9_DSP48E1(__NAME__) """
|
||||
module __NAME__ (
|
||||
output [29:0] ACOUT,
|
||||
output [17:0] BCOUT,
|
||||
|
|
@ -192,6 +192,6 @@ module __NAME__ (
|
|||
parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
|
||||
endmodule
|
||||
"""
|
||||
(* abc_box_id=3000 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT )
|
||||
(* abc_box_id=3001 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT_DPORT )
|
||||
(* abc_box_id=3002 *) `ABC_DSP48E1(\$__ABC_DSP48E1 )
|
||||
(* abc9_box_id=3000 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1_MULT )
|
||||
(* abc9_box_id=3001 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1_MULT_DPORT )
|
||||
(* abc9_box_id=3002 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1 )
|
||||
|
|
@ -20,20 +20,26 @@
|
|||
|
||||
// ============================================================================
|
||||
|
||||
module \$__ABC_ASYNC (input A, S, output Y);
|
||||
module \$__ABC9_ASYNC (input A, S, output Y);
|
||||
assign Y = A;
|
||||
endmodule
|
||||
|
||||
module \$__ABC_FF_ (input D, output Q);
|
||||
module \$__ABC9_FF_ (input D, output Q);
|
||||
assign Q = D;
|
||||
|
||||
module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
|
||||
assign Y = A;
|
||||
endmodule
|
||||
module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
|
||||
assign Y = A;
|
||||
endmodule
|
||||
|
||||
module \$__ABC_REG (input [WIDTH-1:0] I, output [WIDTH-1:0] O, output Q);
|
||||
module \$__ABC9_REG (input [WIDTH-1:0] I, output [WIDTH-1:0] O, output Q);
|
||||
parameter WIDTH = 1;
|
||||
assign O = I;
|
||||
endmodule
|
||||
(* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC_DSP48E1_P_MUX $__ABC_DSP48E1_PCOUT_MUX" *)
|
||||
module \$__ABC_DSP48E1_MUX (
|
||||
(* techmap_celltype = "$__ABC9_DSP48E1_MULT_P_MUX $__ABC9_DSP48E1_MULT_PCOUT_MUX $__ABC9_DSP48E1_MULT_DPORT_P_MUX $__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC9_DSP48E1_P_MUX $__ABC9_DSP48E1_PCOUT_MUX" *)
|
||||
module \$__ABC9_DSP48E1_MUX (
|
||||
input Aq, Bq, Cq, Dq, ADq,
|
||||
input [47:0] I,
|
||||
input Mq,
|
||||
|
|
@ -44,8 +50,8 @@ module \$__ABC_DSP48E1_MUX (
|
|||
assign O = I;
|
||||
endmodule
|
||||
|
||||
(* techmap_celltype = "$__ABC_DSP48E1_MULT $__ABC_DSP48E1_MULT_DPORT $__ABC_DSP48E1" *)
|
||||
module \$__ABC_DSP48E1 (
|
||||
(* techmap_celltype = "$__ABC9_DSP48E1_MULT $__ABC9_DSP48E1_MULT_DPORT $__ABC9_DSP48E1" *)
|
||||
module \$__ABC9_DSP48E1 (
|
||||
(* techmap_autopurge *) output [29:0] ACOUT,
|
||||
(* techmap_autopurge *) output [17:0] BCOUT,
|
||||
(* techmap_autopurge *) output reg CARRYCASCOUT,
|
||||
|
|
@ -101,18 +101,18 @@ FDSE_1 1008 1 5 1
|
|||
# into comb and seq parts, with this box modelling only the former.
|
||||
# Inputs: A S0 S1 S2 S3 S4 S5
|
||||
# Outputs: Y
|
||||
$__ABC_LUT6 2000 0 7 1
|
||||
$__ABC9_LUT6 2000 0 7 1
|
||||
0 642 631 472 407 238 127
|
||||
|
||||
# SLICEM/A6LUT + F7BMUX
|
||||
# Box to emulate comb/seq behaviour of RAMD128
|
||||
# Inputs: A S0 S1 S2 S3 S4 S5 S6
|
||||
# Outputs: DPO SPO
|
||||
$__ABC_LUT7 2001 0 8 1
|
||||
$__ABC9_LUT7 2001 0 8 1
|
||||
0 1047 1036 877 812 643 532 478
|
||||
|
||||
# Boxes used to represent the comb/seq behaviour of DSP48E1
|
||||
# With abc_map.v responsible for disconnecting inputs to
|
||||
# With abc9_map.v responsible for disconnecting inputs to
|
||||
# the combinatorial DSP48E1 model by a register (e.g.
|
||||
# disconnecting A when AREG, MREG or PREG is enabled)
|
||||
# this mux captures the existence of a replacement path
|
||||
|
|
@ -121,7 +121,7 @@ $__ABC_LUT7 2001 0 8 1
|
|||
# the mux at zero time, the combinatorial delay through
|
||||
# these muxes thus represents the clock-to-q delay at
|
||||
# P/PCOUT.
|
||||
$__ABC_DSP48E1_MULT_P_MUX 2100 0 103 48
|
||||
$__ABC9_DSP48E1_MULT_P_MUX 2100 0 103 48
|
||||
# A AD B C D I M P Pq
|
||||
2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
|
||||
2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
|
||||
|
|
@ -171,7 +171,7 @@ $__ABC_DSP48E1_MULT_P_MUX 2100 0 103 48
|
|||
2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
|
||||
2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
|
||||
2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
|
||||
$__ABC_DSP48E1_MULT_PCOUT_MUX 2101 0 103 48
|
||||
$__ABC9_DSP48E1_MULT_PCOUT_MUX 2101 0 103 48
|
||||
# A AD B C D I M P Pq
|
||||
3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
|
||||
3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
|
||||
|
|
@ -221,7 +221,7 @@ $__ABC_DSP48E1_MULT_PCOUT_MUX 2101 0 103 48
|
|||
3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
|
||||
3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
|
||||
3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
|
||||
$__ABC_DSP48E1_MULT_DPORT_P_MUX 2102 0 103 48
|
||||
$__ABC9_DSP48E1_MULT_DPORT_P_MUX 2102 0 103 48
|
||||
# A AD B C D I M P Pq
|
||||
3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
|
||||
3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
|
||||
|
|
@ -271,7 +271,7 @@ $__ABC_DSP48E1_MULT_DPORT_P_MUX 2102 0 103 48
|
|||
3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
|
||||
3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
|
||||
3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
|
||||
$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX 2103 0 103 48
|
||||
$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX 2103 0 103 48
|
||||
# A AD B C D I M P Pq
|
||||
4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
|
||||
4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
|
||||
|
|
@ -321,7 +321,7 @@ $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX 2103 0 103 48
|
|||
4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
|
||||
4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
|
||||
4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
|
||||
$__ABC_DSP48E1_P_MUX 2104 0 103 48
|
||||
$__ABC9_DSP48E1_P_MUX 2104 0 103 48
|
||||
# A AD B C D I M P Pq
|
||||
1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
|
||||
1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
|
||||
|
|
@ -371,7 +371,7 @@ $__ABC_DSP48E1_P_MUX 2104 0 103 48
|
|||
1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
|
||||
1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
|
||||
1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
|
||||
$__ABC_DSP48E1_PCOUT_MUX 2105 0 103 48
|
||||
$__ABC9_DSP48E1_PCOUT_MUX 2105 0 103 48
|
||||
# A AD B C D I M P Pq
|
||||
1780 - 1765 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
|
||||
1780 - 1765 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
|
||||
|
|
@ -422,7 +422,7 @@ $__ABC_DSP48E1_PCOUT_MUX 2105 0 103 48
|
|||
1780 - 1765 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
|
||||
1780 - 1765 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
|
||||
|
||||
$__ABC_DSP48E1_MULT 3000 0 263 154
|
||||
$__ABC9_DSP48E1_MULT 3000 0 263 154
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 - - 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 -
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 - - 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 -
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 - - 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 -
|
||||
|
|
@ -686,7 +686,7 @@ $__ABC_DSP48E1_MULT 3000 0 263 154
|
|||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
||||
$__ABC_DSP48E1_MULT_DPORT 3001 0 263 154
|
||||
$__ABC9_DSP48E1_MULT_DPORT 3001 0 263 154
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 - - 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 -
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 - - 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 -
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 - - 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 -
|
||||
|
|
@ -950,7 +950,7 @@ $__ABC_DSP48E1_MULT_DPORT 3001 0 263 154
|
|||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
||||
$__ABC_DSP48E1 3002 0 263 154
|
||||
$__ABC9_DSP48E1 3002 0 263 154
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 - - 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 -
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 - - 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 -
|
||||
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 - - 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 -
|
||||
|
|
@ -184,12 +184,12 @@ module MUXCY(output O, input CI, DI, S);
|
|||
assign O = S ? CI : DI;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 1, lib_whitebox *)
|
||||
(* abc9_box_id = 1, lib_whitebox *)
|
||||
module MUXF7(output O, input I0, I1, S);
|
||||
assign O = S ? I1 : I0;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 2, lib_whitebox *)
|
||||
(* abc9_box_id = 2, lib_whitebox *)
|
||||
module MUXF8(output O, input I0, I1, S);
|
||||
assign O = S ? I1 : I0;
|
||||
endmodule
|
||||
|
|
@ -198,12 +198,12 @@ module XORCY(output O, input CI, LI);
|
|||
assign O = CI ^ LI;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 4, lib_whitebox *)
|
||||
(* abc9_box_id = 4, lib_whitebox *)
|
||||
module CARRY4(
|
||||
(* abc_carry *)
|
||||
(* abc9_carry *)
|
||||
output [3:0] CO,
|
||||
output [3:0] O,
|
||||
(* abc_carry *)
|
||||
(* abc9_carry *)
|
||||
input CI,
|
||||
input CYINIT,
|
||||
input [3:0] DI, S
|
||||
|
|
@ -240,9 +240,9 @@ endmodule
|
|||
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
|
||||
|
||||
(* abc_box_id=1001, lib_whitebox, abc9_flop *)
|
||||
(* abc9_box_id=1001, lib_whitebox, abc9_flop *)
|
||||
module FDRE (
|
||||
(* abc_arrival=303 *)
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
|
|
@ -261,9 +261,9 @@ module FDRE (
|
|||
wire \$currQ ;
|
||||
reg \$nextQ ;
|
||||
always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
|
||||
`ifdef _ABC
|
||||
`ifdef _ABC9
|
||||
// `abc9' requires that complex flops be split into a combinatorial
|
||||
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
|
||||
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
|
||||
// In order to achieve clock-enable behaviour, the current value
|
||||
// of the sequential output is required which Yosys will
|
||||
// connect to the special `$currQ' wire.
|
||||
|
|
@ -287,9 +287,9 @@ module FDRE (
|
|||
`endif
|
||||
endmodule
|
||||
|
||||
(* abc_box_id=1002, lib_whitebox, abc9_flop *)
|
||||
(* abc9_box_id=1002, lib_whitebox, abc9_flop *)
|
||||
module FDRE_1 (
|
||||
(* abc_arrival=303 *)
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
|
|
@ -300,9 +300,9 @@ module FDRE_1 (
|
|||
wire \$currQ ;
|
||||
reg \$nextQ ;
|
||||
always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ;
|
||||
`ifdef _ABC
|
||||
`ifdef _ABC9
|
||||
// `abc9' requires that complex flops be split into a combinatorial
|
||||
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
|
||||
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
|
||||
// In order to achieve clock-enable behaviour, the current value
|
||||
// of the sequential output is required which Yosys will
|
||||
// connect to the special `$currQ' wire.
|
||||
|
|
@ -323,9 +323,9 @@ module FDRE_1 (
|
|||
`endif
|
||||
endmodule
|
||||
|
||||
(* abc_box_id=1003, lib_whitebox, abc9_flop *)
|
||||
(* abc9_box_id=1003, lib_whitebox, abc9_flop *)
|
||||
module FDCE (
|
||||
(* abc_arrival=303 *)
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
|
|
@ -344,14 +344,14 @@ module FDCE (
|
|||
wire \$currQ ;
|
||||
reg \$nextQ ;
|
||||
always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
|
||||
`ifdef _ABC
|
||||
`ifdef _ABC9
|
||||
// `abc9' requires that complex flops be split into a combinatorial
|
||||
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
|
||||
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
|
||||
// In order to achieve clock-enable behaviour, the current value
|
||||
// of the sequential output is required which Yosys will
|
||||
// connect to the special `$currQ' wire.
|
||||
// Since this is an async flop, async behaviour is also dealt with
|
||||
// using the $_ABC_ASYNC box by abc_map.v
|
||||
// using the $_ABC9_ASYNC box by abc9_map.v
|
||||
|
||||
// Special signal indicating clock domain
|
||||
// (used to partition the module so that `abc9' only performs
|
||||
|
|
@ -374,9 +374,9 @@ module FDCE (
|
|||
`endif
|
||||
endmodule
|
||||
|
||||
(* abc_box_id=1004, lib_whitebox, abc9_flop *)
|
||||
(* abc9_box_id=1004, lib_whitebox, abc9_flop *)
|
||||
module FDCE_1 (
|
||||
(* abc_arrival=303 *)
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
|
|
@ -387,14 +387,14 @@ module FDCE_1 (
|
|||
wire \$currQ ;
|
||||
reg \$nextQ ;
|
||||
always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
|
||||
`ifdef _ABC
|
||||
`ifdef _ABC9
|
||||
// `abc9' requires that complex flops be split into a combinatorial
|
||||
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
|
||||
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
|
||||
// In order to achieve clock-enable behaviour, the current value
|
||||
// of the sequential output is required which Yosys will
|
||||
// connect to the special `$currQ' wire.
|
||||
// Since this is an async flop, async behaviour is also dealt with
|
||||
// using the $_ABC_ASYNC box by abc_map.v
|
||||
// using the $_ABC9_ASYNC box by abc9_map.v
|
||||
|
||||
// Special signal indicating clock domain
|
||||
// (used to partition the module so that `abc9' only performs
|
||||
|
|
@ -412,9 +412,9 @@ module FDCE_1 (
|
|||
`endif
|
||||
endmodule
|
||||
|
||||
(* abc_box_id=1005, lib_whitebox, abc9_flop *)
|
||||
(* abc9_box_id=1005, lib_whitebox, abc9_flop *)
|
||||
module FDPE (
|
||||
(* abc_arrival=303 *)
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
|
|
@ -433,14 +433,14 @@ module FDPE (
|
|||
wire \$currQ ;
|
||||
reg \$nextQ ;
|
||||
always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
|
||||
`ifdef _ABC
|
||||
`ifdef _ABC9
|
||||
// `abc9' requires that complex flops be split into a combinatorial
|
||||
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
|
||||
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
|
||||
// In order to achieve clock-enable behaviour, the current value
|
||||
// of the sequential output is required which Yosys will
|
||||
// connect to the special `$currQ' wire.
|
||||
// Since this is an async flop, async behaviour is also dealt with
|
||||
// using the $_ABC_ASYNC box by abc_map.v
|
||||
// using the $_ABC9_ASYNC box by abc9_map.v
|
||||
|
||||
// Special signal indicating clock domain
|
||||
// (used to partition the module so that `abc9' only performs
|
||||
|
|
@ -463,9 +463,9 @@ module FDPE (
|
|||
`endif
|
||||
endmodule
|
||||
|
||||
(* abc_box_id=1006, lib_whitebox, abc9_flop *)
|
||||
(* abc9_box_id=1006, lib_whitebox, abc9_flop *)
|
||||
module FDPE_1 (
|
||||
(* abc_arrival=303 *)
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
|
|
@ -476,14 +476,14 @@ module FDPE_1 (
|
|||
wire \$currQ ;
|
||||
reg \$nextQ ;
|
||||
always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
|
||||
`ifdef _ABC
|
||||
`ifdef _ABC9
|
||||
// `abc9' requires that complex flops be split into a combinatorial
|
||||
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
|
||||
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
|
||||
// In order to achieve clock-enable behaviour, the current value
|
||||
// of the sequential output is required which Yosys will
|
||||
// connect to the special `$currQ' wire.
|
||||
// Since this is an async flop, async behaviour is also dealt with
|
||||
// using the $_ABC_ASYNC box by abc_map.v
|
||||
// using the $_ABC9_ASYNC box by abc9_map.v
|
||||
|
||||
// Special signal indicating clock domain
|
||||
// (used to partition the module so that `abc9' only performs
|
||||
|
|
@ -501,9 +501,9 @@ module FDPE_1 (
|
|||
`endif
|
||||
endmodule
|
||||
|
||||
(* abc_box_id=1007, lib_whitebox, abc9_flop *)
|
||||
(* abc9_box_id=1007, lib_whitebox, abc9_flop *)
|
||||
module FDSE (
|
||||
(* abc_arrival=303 *)
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
|
|
@ -522,9 +522,9 @@ module FDSE (
|
|||
wire \$currQ ;
|
||||
reg \$nextQ ;
|
||||
always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
|
||||
`ifdef _ABC
|
||||
`ifdef _ABC9
|
||||
// `abc9' requires that complex flops be split into a combinatorial
|
||||
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
|
||||
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
|
||||
// In order to achieve clock-enable behaviour, the current value
|
||||
// of the sequential output is required which Yosys will
|
||||
// connect to the special `$currQ' wire.
|
||||
|
|
@ -548,9 +548,9 @@ module FDSE (
|
|||
`endif
|
||||
endmodule
|
||||
|
||||
(* abc_box_id=1008, lib_whitebox, abc9_flop *)
|
||||
(* abc9_box_id=1008, lib_whitebox, abc9_flop *)
|
||||
module FDSE_1 (
|
||||
(* abc_arrival=303 *)
|
||||
(* abc9_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
|
|
@ -561,9 +561,9 @@ module FDSE_1 (
|
|||
wire \$currQ ;
|
||||
reg \$nextQ ;
|
||||
always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ;
|
||||
`ifdef _ABC
|
||||
`ifdef _ABC9
|
||||
// `abc9' requires that complex flops be split into a combinatorial
|
||||
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
|
||||
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
|
||||
// In order to achieve clock-enable behaviour, the current value
|
||||
// of the sequential output is required which Yosys will
|
||||
// connect to the special `$currQ' wire.
|
||||
|
|
@ -630,7 +630,7 @@ endmodule
|
|||
|
||||
module RAM32X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
(* abc_arrival=1153 *)
|
||||
(* abc9_arrival=1153 *)
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
|
|
@ -653,7 +653,7 @@ endmodule
|
|||
|
||||
module RAM64X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
(* abc_arrival=1153 *)
|
||||
(* abc9_arrival=1153 *)
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
|
|
@ -676,7 +676,7 @@ endmodule
|
|||
|
||||
module RAM128X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
(* abc_arrival=1153 *)
|
||||
(* abc9_arrival=1153 *)
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
|
|
@ -696,7 +696,7 @@ endmodule
|
|||
|
||||
module SRL16E (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
|
||||
(* abc_arrival=1472 *)
|
||||
(* abc9_arrival=1472 *)
|
||||
output Q,
|
||||
input A0, A1, A2, A3, CE,
|
||||
(* clkbuf_sink *)
|
||||
|
|
@ -744,9 +744,9 @@ endmodule
|
|||
|
||||
module SRLC32E (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
|
||||
(* abc_arrival=1472 *)
|
||||
(* abc9_arrival=1472 *)
|
||||
output Q,
|
||||
(* abc_arrival=1114 *)
|
||||
(* abc9_arrival=1114 *)
|
||||
output Q31,
|
||||
input [4:0] A,
|
||||
input CE,
|
||||
|
|
|
|||
|
|
@ -474,13 +474,14 @@ struct SynthXilinxPass : public ScriptPass
|
|||
run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut'; option for '-retime')");
|
||||
else if (abc9) {
|
||||
if (family != "xc7")
|
||||
log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
|
||||
run("techmap -map +/xilinx/abc_map.v -max_iter 1");
|
||||
run("read_verilog -icells -lib +/xilinx/abc_model.v");
|
||||
log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
|
||||
"will use timing for 'xc7' instead.\n", family.c_str());
|
||||
run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
|
||||
run("read_verilog -icells -lib +/xilinx/abc9_model.v");
|
||||
if (nowidelut)
|
||||
run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
|
||||
run("abc9 -lut +/xilinx/abc9_xc7_nowide.lut -box +/xilinx/abc9_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
|
||||
else
|
||||
run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
|
||||
run("abc9 -lut +/xilinx/abc9_xc7.lut -box +/xilinx/abc9_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
|
||||
}
|
||||
else {
|
||||
if (nowidelut)
|
||||
|
|
@ -498,7 +499,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
if (help_mode)
|
||||
techmap_args += " [-map " + ff_map_file + "]";
|
||||
else if (abc9)
|
||||
techmap_args += " -map +/xilinx/abc_unmap.v";
|
||||
techmap_args += " -map +/xilinx/abc9_unmap.v";
|
||||
else
|
||||
techmap_args += " -map " + ff_map_file;
|
||||
run("techmap " + techmap_args);
|
||||
|
|
|
|||
|
|
@ -19,9 +19,13 @@ module RAMB8BWER (
|
|||
input [1:0] WEAWEL,
|
||||
input [1:0] WEBWEU,
|
||||
|
||||
/* (* abc9_arrival=<TODO> *) */
|
||||
output [15:0] DOADO,
|
||||
/* (* abc9_arrival=<TODO> *) */
|
||||
output [15:0] DOBDO,
|
||||
/* (* abc9_arrival=<TODO> *) */
|
||||
output [1:0] DOPADOP,
|
||||
/* (* abc9_arrival=<TODO> *) */
|
||||
output [1:0] DOPBDOP
|
||||
);
|
||||
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
|
@ -109,9 +113,13 @@ module RAMB16BWER (
|
|||
input [3:0] WEA,
|
||||
input [3:0] WEB,
|
||||
|
||||
/* (* abc9_arrival=<TODO> *) */
|
||||
output [31:0] DOA,
|
||||
/* (* abc9_arrival=<TODO> *) */
|
||||
output [31:0] DOB,
|
||||
/* (* abc9_arrival=<TODO> *) */
|
||||
output [3:0] DOPA,
|
||||
/* (* abc9_arrival=<TODO> *) */
|
||||
output [3:0] DOPB
|
||||
);
|
||||
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
|
|
|||
|
|
@ -31,13 +31,13 @@ module RAMB18E1 (
|
|||
input [1:0] WEA,
|
||||
input [3:0] WEBWE,
|
||||
|
||||
(* abc_arrival=2454 *)
|
||||
(* abc9_arrival=2454 *)
|
||||
output [15:0] DOADO,
|
||||
(* abc_arrival=2454 *)
|
||||
(* abc9_arrival=2454 *)
|
||||
output [15:0] DOBDO,
|
||||
(* abc_arrival=2454 *)
|
||||
(* abc9_arrival=2454 *)
|
||||
output [1:0] DOPADOP,
|
||||
(* abc_arrival=2454 *)
|
||||
(* abc9_arrival=2454 *)
|
||||
output [1:0] DOPBDOP
|
||||
);
|
||||
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
|
@ -169,13 +169,13 @@ module RAMB36E1 (
|
|||
input [3:0] WEA,
|
||||
input [7:0] WEBWE,
|
||||
|
||||
(* abc_arrival=2454 *)
|
||||
(* abc9_arrival=2454 *)
|
||||
output [31:0] DOADO,
|
||||
(* abc_arrival=2454 *)
|
||||
(* abc9_arrival=2454 *)
|
||||
output [31:0] DOBDO,
|
||||
(* abc_arrival=2454 *)
|
||||
(* abc9_arrival=2454 *)
|
||||
output [3:0] DOPADOP,
|
||||
(* abc_arrival=2454 *)
|
||||
(* abc9_arrival=2454 *)
|
||||
output [3:0] DOPBDOP
|
||||
);
|
||||
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
|
|
|||
Loading…
Reference in New Issue