From c0f54d3fd5e2492afbe1717a67ea78f3be7f6b39 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 4 Oct 2019 10:34:16 -0700
Subject: [PATCH 1/4] Ohmilord this wasn't added all this time!?!

---
 techlibs/ice40/abc_model.v | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 techlibs/ice40/abc_model.v

diff --git a/techlibs/ice40/abc_model.v b/techlibs/ice40/abc_model.v
new file mode 100644
index 000000000..89961b51d
--- /dev/null
+++ b/techlibs/ice40/abc_model.v
@@ -0,0 +1,29 @@
+(* abc9_box_id = 1, lib_whitebox *)
+module \$__ICE40_CARRY_WRAPPER (
+	(* abc_carry *)
+	output CO,
+	output O,
+	input A, B,
+	(* abc_carry *)
+	input CI,
+	input I0, I3
+);
+	parameter LUT = 0;
+	SB_CARRY carry (
+		.I0(A),
+		.I1(B),
+		.CI(CI),
+		.CO(CO)
+	);
+	SB_LUT4 #(
+		.LUT_INIT(LUT)
+	) adder (
+		.I0(I0),
+		.I1(A),
+		.I2(B),
+		.I3(I3),
+		.O(O)
+	);
+endmodule
+
+

From 4e11782cde412ce80ee8125dd9d55fe21945737f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 4 Oct 2019 10:36:02 -0700
Subject: [PATCH 2/4] Oops

---
 techlibs/ice40/abc_model.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/ice40/abc_model.v b/techlibs/ice40/abc_model.v
index 89961b51d..8e1827043 100644
--- a/techlibs/ice40/abc_model.v
+++ b/techlibs/ice40/abc_model.v
@@ -1,4 +1,4 @@
-(* abc9_box_id = 1, lib_whitebox *)
+(* abc_box_id = 1, lib_whitebox *)
 module \$__ICE40_CARRY_WRAPPER (
 	(* abc_carry *)
 	output CO,

From 9fef1df3c1431cff2e097a10a502f77f04986a60 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 4 Oct 2019 10:48:44 -0700
Subject: [PATCH 3/4] Panic over. Model was elsewhere. Re-arrange for
 consistency

---
 techlibs/ecp5/synth_ecp5.cc   |  1 +
 techlibs/ice40/Makefile.inc   |  1 +
 techlibs/ice40/abc_model.v    |  2 --
 techlibs/ice40/cells_sim.v    | 28 ----------------------------
 techlibs/ice40/synth_ice40.cc |  3 ++-
 5 files changed, 4 insertions(+), 31 deletions(-)

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 1f5b1cb6b..67d2f483c 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -311,6 +311,7 @@ struct SynthEcp5Pass : public ScriptPass
 			run("techmap " + techmap_args);
 
 			if (abc9) {
+				run("read_verilog -icells -lib +/ecp5/abc_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
 				else
diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 92a9956ea..0fbca9034 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,6 +28,7 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_model.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box))
diff --git a/techlibs/ice40/abc_model.v b/techlibs/ice40/abc_model.v
index 8e1827043..fe31b8811 100644
--- a/techlibs/ice40/abc_model.v
+++ b/techlibs/ice40/abc_model.v
@@ -25,5 +25,3 @@ module \$__ICE40_CARRY_WRAPPER (
 		.O(O)
 	);
 endmodule
-
-
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 8e5e0358e..16a893226 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -145,34 +145,6 @@ module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
-(* abc_box_id = 1, lib_whitebox *)
-module \$__ICE40_CARRY_WRAPPER (
-	(* abc_carry *)
-	output CO,
-	output O,
-	input A, B,
-	(* abc_carry *)
-	input CI,
-	input I0, I3
-);
-	parameter LUT = 0;
-	SB_CARRY carry (
-		.I0(A),
-		.I1(B),
-		.CI(CI),
-		.CO(CO)
-	);
-	SB_LUT4 #(
-		.LUT_INIT(LUT)
-	) adder (
-		.I0(I0),
-		.I1(A),
-		.I2(B),
-		.I3(I3),
-		.O(O)
-	);
-endmodule
-
 // Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
 //                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
 //                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 841f10244..2e4684c19 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -245,7 +245,7 @@ struct SynthIce40Pass : public ScriptPass
 				define = "-D ICE40_U";
 			else
 				define = "-D ICE40_HX";
-			run("read_verilog -icells " + define + " -lib +/ice40/cells_sim.v");
+			run("read_verilog " + define + " -lib +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -349,6 +349,7 @@ struct SynthIce40Pass : public ScriptPass
 			}
 			if (!noabc) {
 				if (abc == "abc9") {
+					run("read_verilog -icells -lib +/ice40/abc_model.v");
 					int wire_delay;
 					if (device_opt == "lp")
 						wire_delay = 400;

From aae2b9fd9c8dc915fadacc24962436dd7aedff36 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 4 Oct 2019 11:04:10 -0700
Subject: [PATCH 4/4] Rename abc_* names/attributes to more precisely be abc9_*

---
 backends/aiger/xaiger.cc                      |  18 +-
 frontends/aiger/aigerparse.cc                 |   8 +-
 passes/techmap/abc9.cc                        | 130 +++++++--------
 techlibs/ecp5/Makefile.inc                    |  12 +-
 techlibs/ecp5/{abc_5g.box => abc9_5g.box}     |   2 +-
 techlibs/ecp5/{abc_5g.lut => abc9_5g.lut}     |   0
 .../{abc_5g_nowide.lut => abc9_5g_nowide.lut} |   0
 techlibs/ecp5/{abc_map.v => abc9_map.v}       |   2 +-
 techlibs/ecp5/abc9_model.v                    |   5 +
 techlibs/ecp5/{abc_unmap.v => abc9_unmap.v}   |   2 +-
 techlibs/ecp5/abc_model.v                     |   5 -
 techlibs/ecp5/cells_sim.v                     |  12 +-
 techlibs/ecp5/synth_ecp5.cc                   |  10 +-
 techlibs/ice40/Makefile.inc                   |  14 +-
 techlibs/ice40/{abc_hx.box => abc9_hx.box}    |   0
 techlibs/ice40/{abc_hx.lut => abc9_hx.lut}    |   0
 techlibs/ice40/{abc_lp.box => abc9_lp.box}    |   0
 techlibs/ice40/{abc_lp.lut => abc9_lp.lut}    |   0
 techlibs/ice40/{abc_model.v => abc9_model.v}  |   6 +-
 techlibs/ice40/{abc_u.box => abc9_u.box}      |   0
 techlibs/ice40/{abc_u.lut => abc9_u.lut}      |   0
 techlibs/ice40/cells_sim.v                    | 157 +++++++++---------
 techlibs/ice40/synth_ice40.cc                 |   4 +-
 techlibs/xilinx/Makefile.inc                  |  12 +-
 techlibs/xilinx/{abc_map.v => abc9_map.v}     |  66 ++++----
 techlibs/xilinx/{abc_model.v => abc9_model.v} |  40 ++---
 techlibs/xilinx/{abc_unmap.v => abc9_unmap.v} |  14 +-
 techlibs/xilinx/{abc_xc7.box => abc9_xc7.box} |  24 +--
 techlibs/xilinx/{abc_xc7.lut => abc9_xc7.lut} |   0
 ...abc_xc7_nowide.lut => abc9_xc7_nowide.lut} |   0
 techlibs/xilinx/cells_sim.v                   |  38 ++---
 techlibs/xilinx/synth_xilinx.cc               |  13 +-
 techlibs/xilinx/xc6s_brams_bb.v               |   8 +
 techlibs/xilinx/xc7_brams_bb.v                |  16 +-
 34 files changed, 313 insertions(+), 305 deletions(-)
 rename techlibs/ecp5/{abc_5g.box => abc9_5g.box} (96%)
 rename techlibs/ecp5/{abc_5g.lut => abc9_5g.lut} (100%)
 rename techlibs/ecp5/{abc_5g_nowide.lut => abc9_5g_nowide.lut} (100%)
 rename techlibs/ecp5/{abc_map.v => abc9_map.v} (89%)
 create mode 100644 techlibs/ecp5/abc9_model.v
 rename techlibs/ecp5/{abc_unmap.v => abc9_unmap.v} (52%)
 delete mode 100644 techlibs/ecp5/abc_model.v
 rename techlibs/ice40/{abc_hx.box => abc9_hx.box} (100%)
 rename techlibs/ice40/{abc_hx.lut => abc9_hx.lut} (100%)
 rename techlibs/ice40/{abc_lp.box => abc9_lp.box} (100%)
 rename techlibs/ice40/{abc_lp.lut => abc9_lp.lut} (100%)
 rename techlibs/ice40/{abc_model.v => abc9_model.v} (79%)
 rename techlibs/ice40/{abc_u.box => abc9_u.box} (100%)
 rename techlibs/ice40/{abc_u.lut => abc9_u.lut} (100%)
 rename techlibs/xilinx/{abc_map.v => abc9_map.v} (88%)
 rename techlibs/xilinx/{abc_model.v => abc9_model.v} (83%)
 rename techlibs/xilinx/{abc_unmap.v => abc9_unmap.v} (92%)
 rename techlibs/xilinx/{abc_xc7.box => abc9_xc7.box} (99%)
 rename techlibs/xilinx/{abc_xc7.lut => abc9_xc7.lut} (100%)
 rename techlibs/xilinx/{abc_xc7_nowide.lut => abc9_xc7_nowide.lut} (100%)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 4018cc9de..46890b071 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -203,7 +203,7 @@ struct XAigerWriter
 		//       box ordering, but not individual AIG cells
 		dict<SigBit, pool<IdString>> bit_drivers, bit_users;
 		TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
-		bool abc_box_seen = false;
+		bool abc9_box_seen = false;
 
 		for (auto cell : module->selected_cells()) {
 			if (cell->type == "$_NOT_")
@@ -242,8 +242,8 @@ struct XAigerWriter
 			log_assert(!holes_mode);
 
 			RTLIL::Module* inst_module = module->design->module(cell->type);
-			if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
-				abc_box_seen = true;
+			if (inst_module && inst_module->attributes.count("\\abc9_box_id")) {
+				abc9_box_seen = true;
 
 				if (!holes_mode) {
 					toposort.node(cell->name);
@@ -291,10 +291,10 @@ struct XAigerWriter
 					if (is_output) {
 						int arrival = 0;
 						if (port_wire) {
-							auto it = port_wire->attributes.find("\\abc_arrival");
+							auto it = port_wire->attributes.find("\\abc9_arrival");
 							if (it != port_wire->attributes.end()) {
 								if (it->second.flags != 0)
-									log_error("Attribute 'abc_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
+									log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
 								arrival = it->second.as_int();
 							}
 						}
@@ -318,7 +318,7 @@ struct XAigerWriter
 			//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
 		}
 
-		if (abc_box_seen) {
+		if (abc9_box_seen) {
 			for (auto &it : bit_users)
 				if (bit_drivers.count(it.first))
 					for (auto driver_cell : bit_drivers.at(it.first))
@@ -347,7 +347,7 @@ struct XAigerWriter
 				log_assert(cell);
 
 				RTLIL::Module* box_module = module->design->module(cell->type);
-				if (!box_module || !box_module->attributes.count("\\abc_box_id"))
+				if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
 					continue;
 
 				bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
@@ -398,7 +398,7 @@ struct XAigerWriter
 						else {
 							Wire *wire = module->addWire(NEW_ID, GetSize(w));
 							if (blackbox)
-								wire->set_bool_attribute(ID(abc_padding));
+								wire->set_bool_attribute(ID(abc9_padding));
 							rhs = wire;
 							cell->setPort(port_name, rhs);
 						}
@@ -666,7 +666,7 @@ struct XAigerWriter
 
 				write_h_buffer(box_inputs);
 				write_h_buffer(box_outputs);
-				write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int());
+				write_h_buffer(box_module->attributes.at("\\abc9_box_id").as_int());
 				write_h_buffer(box_count++);
 			}
 
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 5a1da4db1..cf060193d 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -740,22 +740,22 @@ void AigerReader::post_process()
 		log_assert(box_module);
 
 		if (seen_boxes.insert(cell->type).second) {
-			auto it = box_module->attributes.find("\\abc_carry");
+			auto it = box_module->attributes.find("\\abc9_carry");
 			if (it != box_module->attributes.end()) {
 				RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
 				auto carry_in_out = it->second.decode_string();
 				auto pos = carry_in_out.find(',');
 				if (pos == std::string::npos)
-					log_error("'abc_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type));
+					log_error("'abc9_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type));
 				auto carry_in_name = RTLIL::escape_id(carry_in_out.substr(0, pos));
 				carry_in = box_module->wire(carry_in_name);
 				if (!carry_in || !carry_in->port_input)
-					log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str());
+					log_error("'abc9_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str());
 
 				auto carry_out_name = RTLIL::escape_id(carry_in_out.substr(pos+1));
 				carry_out = box_module->wire(carry_out_name);
 				if (!carry_out || !carry_out->port_output)
-					log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str());
+					log_error("'abc9_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str());
 
 				auto &ports = box_module->ports;
 				for (auto jt = ports.begin(); jt != ports.end(); ) {
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 09d6e9670..1ebdaa29e 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -71,21 +71,21 @@ RTLIL::Module *module;
 bool clk_polarity, en_polarity;
 RTLIL::SigSpec clk_sig, en_sig;
 
-inline std::string remap_name(RTLIL::IdString abc_name)
+inline std::string remap_name(RTLIL::IdString abc9_name)
 {
-	return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1);
+	return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
 }
 
 void handle_loops(RTLIL::Design *design)
 {
-	Pass::call(design, "scc -set_attr abc_scc_id {}");
+	Pass::call(design, "scc -set_attr abc9_scc_id {}");
 
 	// For every unique SCC found, (arbitrarily) find the first
 	// cell in the component, and select (and mark) all its output
 	// wires
 	pool<RTLIL::Const> ids_seen;
 	for (auto cell : module->cells()) {
-		auto it = cell->attributes.find(ID(abc_scc_id));
+		auto it = cell->attributes.find(ID(abc9_scc_id));
 		if (it != cell->attributes.end()) {
 			auto r = ids_seen.insert(it->second);
 			if (r.second) {
@@ -105,7 +105,7 @@ void handle_loops(RTLIL::Design *design)
 							log_assert(w->port_input);
 							log_assert(b.offset < GetSize(w));
 						}
-						w->set_bool_attribute(ID(abc_scc_break));
+						w->set_bool_attribute(ID(abc9_scc_break));
 						module->swap_names(b.wire, w);
 						c.second = RTLIL::SigBit(w, b.offset);
 					}
@@ -118,7 +118,7 @@ void handle_loops(RTLIL::Design *design)
 	module->fixup_ports();
 }
 
-std::string add_echos_to_abc_cmd(std::string str)
+std::string add_echos_to_abc9_cmd(std::string str)
 {
 	std::string new_str, token;
 	for (size_t i = 0; i < str.size(); i++) {
@@ -140,7 +140,7 @@ std::string add_echos_to_abc_cmd(std::string str)
 	return new_str;
 }
 
-std::string fold_abc_cmd(std::string str)
+std::string fold_abc9_cmd(std::string str)
 {
 	std::string token, new_str = "          ";
 	int char_counter = 10;
@@ -184,7 +184,7 @@ std::string replace_tempdir(std::string text, std::string tempdir_name, bool sho
 	return text;
 }
 
-struct abc_output_filter
+struct abc9_output_filter
 {
 	bool got_cr;
 	int escape_seq_state;
@@ -192,7 +192,7 @@ struct abc_output_filter
 	std::string tempdir_name;
 	bool show_tempdir;
 
-	abc_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir)
+	abc9_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir)
 	{
 		got_cr = false;
 		escape_seq_state = 0;
@@ -293,68 +293,68 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 	log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
 			module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
 
-	std::string abc_script;
+	std::string abc9_script;
 
 	if (!lut_costs.empty()) {
-		abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
+		abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
 		if (!box_file.empty())
-			abc_script += stringf("read_box -v %s; ", box_file.c_str());
+			abc9_script += stringf("read_box -v %s; ", box_file.c_str());
 	}
 	else
 	if (!lut_file.empty()) {
-		abc_script += stringf("read_lut %s; ", lut_file.c_str());
+		abc9_script += stringf("read_lut %s; ", lut_file.c_str());
 		if (!box_file.empty())
-			abc_script += stringf("read_box -v %s; ", box_file.c_str());
+			abc9_script += stringf("read_box -v %s; ", box_file.c_str());
 	}
 	else
 		log_abort();
 
-	abc_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
+	abc9_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
 
 	if (!script_file.empty()) {
 		if (script_file[0] == '+') {
 			for (size_t i = 1; i < script_file.size(); i++)
 				if (script_file[i] == '\'')
-					abc_script += "'\\''";
+					abc9_script += "'\\''";
 				else if (script_file[i] == ',')
-					abc_script += " ";
+					abc9_script += " ";
 				else
-					abc_script += script_file[i];
+					abc9_script += script_file[i];
 		} else
-			abc_script += stringf("source %s", script_file.c_str());
+			abc9_script += stringf("source %s", script_file.c_str());
 	} else if (!lut_costs.empty() || !lut_file.empty()) {
 		//bool all_luts_cost_same = true;
 		//for (int this_cost : lut_costs)
 		//	if (this_cost != lut_costs.front())
 		//		all_luts_cost_same = false;
-		abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
+		abc9_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
 		//if (all_luts_cost_same && !fast_mode)
-		//	abc_script += "; lutpack {S}";
+		//	abc9_script += "; lutpack {S}";
 	} else
 		log_abort();
 
 	//if (script_file.empty() && !delay_target.empty())
-	//	for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1))
-	//		abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8);
+	//	for (size_t pos = abc9_script.find("dretime;"); pos != std::string::npos; pos = abc9_script.find("dretime;", pos+1))
+	//		abc9_script = abc9_script.substr(0, pos) + "dretime; retime -o {D};" + abc9_script.substr(pos+8);
 
-	for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
-		abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
+	for (size_t pos = abc9_script.find("{D}"); pos != std::string::npos; pos = abc9_script.find("{D}", pos))
+		abc9_script = abc9_script.substr(0, pos) + delay_target + abc9_script.substr(pos+3);
 
-	//for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
-	//	abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
+	//for (size_t pos = abc9_script.find("{S}"); pos != std::string::npos; pos = abc9_script.find("{S}", pos))
+	//	abc9_script = abc9_script.substr(0, pos) + lutin_shared + abc9_script.substr(pos+3);
 
-	for (size_t pos = abc_script.find("{W}"); pos != std::string::npos; pos = abc_script.find("{W}", pos))
-		abc_script = abc_script.substr(0, pos) + wire_delay + abc_script.substr(pos+3);
+	for (size_t pos = abc9_script.find("{W}"); pos != std::string::npos; pos = abc9_script.find("{W}", pos))
+		abc9_script = abc9_script.substr(0, pos) + wire_delay + abc9_script.substr(pos+3);
 
-	abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
-	abc_script = add_echos_to_abc_cmd(abc_script);
+	abc9_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
+	abc9_script = add_echos_to_abc9_cmd(abc9_script);
 
-	for (size_t i = 0; i+1 < abc_script.size(); i++)
-		if (abc_script[i] == ';' && abc_script[i+1] == ' ')
-			abc_script[i+1] = '\n';
+	for (size_t i = 0; i+1 < abc9_script.size(); i++)
+		if (abc9_script[i] == ';' && abc9_script[i+1] == ' ')
+			abc9_script[i+1] = '\n';
 
 	FILE *f = fopen(stringf("%s/abc.script", tempdir_name.c_str()).c_str(), "wt");
-	fprintf(f, "%s\n", abc_script.c_str());
+	fprintf(f, "%s\n", abc9_script.c_str());
 	fclose(f);
 
 	if (dff_mode || !clk_str.empty())
@@ -420,7 +420,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 		// the expose operation -- remove them from PO/PI
 		// and re-connecting them back together
 		for (auto wire : module->wires()) {
-			auto it = wire->attributes.find(ID(abc_scc_break));
+			auto it = wire->attributes.find(ID(abc9_scc_break));
 			if (it != wire->attributes.end()) {
 				wire->attributes.erase(it);
 				log_assert(wire->port_output);
@@ -450,22 +450,22 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 		log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
 
 #ifndef YOSYS_LINK_ABC
-		abc_output_filter filt(tempdir_name, show_tempdir);
-		int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
+		abc9_output_filter filt(tempdir_name, show_tempdir);
+		int ret = run_command(buffer, std::bind(&abc9_output_filter::next_line, filt, std::placeholders::_1));
 #else
 		// These needs to be mutable, supposedly due to getopt
-		char *abc_argv[5];
+		char *abc9_argv[5];
 		string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str());
-		abc_argv[0] = strdup(exe_file.c_str());
-		abc_argv[1] = strdup("-s");
-		abc_argv[2] = strdup("-f");
-		abc_argv[3] = strdup(tmp_script_name.c_str());
-		abc_argv[4] = 0;
-		int ret = Abc_RealMain(4, abc_argv);
-		free(abc_argv[0]);
-		free(abc_argv[1]);
-		free(abc_argv[2]);
-		free(abc_argv[3]);
+		abc9_argv[0] = strdup(exe_file.c_str());
+		abc9_argv[1] = strdup("-s");
+		abc9_argv[2] = strdup("-f");
+		abc9_argv[3] = strdup(tmp_script_name.c_str());
+		abc9_argv[4] = 0;
+		int ret = Abc_RealMain(4, abc9_argv);
+		free(abc9_argv[0]);
+		free(abc9_argv[1]);
+		free(abc9_argv[2]);
+		free(abc9_argv[3]);
 #endif
 		if (ret != 0)
 			log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
@@ -513,7 +513,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 			signal = std::move(bits);
 		}
 
-		dict<IdString, bool> abc_box;
+		dict<IdString, bool> abc9_box;
 		vector<RTLIL::Cell*> boxes;
 		for (const auto &it : module->cells_) {
 			auto cell = it.second;
@@ -521,10 +521,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 				module->remove(cell);
 				continue;
 			}
-			auto jt = abc_box.find(cell->type);
-			if (jt == abc_box.end()) {
+			auto jt = abc9_box.find(cell->type);
+			if (jt == abc9_box.end()) {
 				RTLIL::Module* box_module = design->module(cell->type);
-				jt = abc_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc_box_id)))).first;
+				jt = abc9_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc9_box_id)))).first;
 			}
 			if (jt->second)
 				boxes.emplace_back(cell);
@@ -648,7 +648,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 					if (!conn.second.is_wire())
 						continue;
 					Wire *wire = conn.second.as_wire();
-					if (!wire->get_bool_attribute(ID(abc_padding)))
+					if (!wire->get_bool_attribute(ID(abc9_padding)))
 						continue;
 					cell->unsetPort(conn.first);
 					log_debug("Dropping padded port connection for %s (%s) .%s (%s )\n", log_id(cell), cell->type.c_str(), log_id(conn.first), log_signal(conn.second));
@@ -827,17 +827,17 @@ struct Abc9Pass : public Pass {
 		log("        if no -script parameter is given, the following scripts are used:\n");
 		log("\n");
 		log("        for -lut/-luts (only one LUT size):\n");
-		log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT /*"; lutpack {S}"*/).c_str());
+		log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT /*"; lutpack {S}"*/).c_str());
 		log("\n");
 		log("        for -lut/-luts (different LUT sizes):\n");
-		log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str());
+		log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT).c_str());
 		log("\n");
 		log("    -fast\n");
 		log("        use different default scripts that are slightly faster (at the cost\n");
 		log("        of output quality):\n");
 		log("\n");
 		log("        for -lut/-luts:\n");
-		log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str());
+		log("%s\n", fold_abc9_cmd(ABC_FAST_COMMAND_LUT).c_str());
 		log("\n");
 		log("    -D <picoseconds>\n");
 		log("        set delay target. the string {D} in the default scripts above is\n");
@@ -1057,7 +1057,7 @@ struct Abc9Pass : public Pass {
 
 		dict<int,IdString> box_lookup;
 		for (auto m : design->modules()) {
-			auto it = m->attributes.find(ID(abc_box_id));
+			auto it = m->attributes.find(ID(abc9_box_id));
 			if (it == m->attributes.end())
 				continue;
 			if (m->name.begins_with("$paramod"))
@@ -1065,7 +1065,7 @@ struct Abc9Pass : public Pass {
 			auto id = it->second.as_int();
 			auto r = box_lookup.insert(std::make_pair(id, m->name));
 			if (!r.second)
-				log_error("Module '%s' has the same abc_box_id = %d value as '%s'.\n",
+				log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
 						log_id(m), id, log_id(r.first->second));
 			log_assert(r.second);
 
@@ -1073,24 +1073,24 @@ struct Abc9Pass : public Pass {
 			for (auto p : m->ports) {
 				auto w = m->wire(p);
 				log_assert(w);
-				if (w->attributes.count(ID(abc_carry))) {
+				if (w->attributes.count(ID(abc9_carry))) {
 					if (w->port_input) {
 						if (carry_in)
-							log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m));
+							log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
 						carry_in = w;
 					}
 					else if (w->port_output) {
 						if (carry_out)
-							log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m));
+							log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
 						carry_out = w;
 					}
 				}
 			}
 			if (carry_in || carry_out) {
 				if (carry_in && !carry_out)
-					log_error("Module '%s' contains an 'abc_carry' input port but no output port.\n", log_id(m));
+					log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
 				if (!carry_in && carry_out)
-					log_error("Module '%s' contains an 'abc_carry' output port but no input port.\n", log_id(m));
+					log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
 				// Make carry_in the last PI, and carry_out the last PO
 				//   since ABC requires it this way
 				auto &ports = m->ports;
@@ -1118,7 +1118,7 @@ struct Abc9Pass : public Pass {
 
 		for (auto mod : design->selected_modules())
 		{
-			if (mod->attributes.count(ID(abc_box_id)))
+			if (mod->attributes.count(ID(abc9_box_id)))
 				continue;
 
 			if (mod->processes.size() > 0) {
diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index b03da164c..5832d07ee 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -15,12 +15,12 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
 
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_map.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_unmap.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_model.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_unmap.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_model.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.box))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.lut))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g_nowide.lut))
 
 EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
 .SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc9_5g.box
similarity index 96%
rename from techlibs/ecp5/abc_5g.box
rename to techlibs/ecp5/abc9_5g.box
index a336b4a85..2bc945a54 100644
--- a/techlibs/ecp5/abc_5g.box
+++ b/techlibs/ecp5/abc9_5g.box
@@ -18,7 +18,7 @@ CCU2C   1      1   9      3
 # Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
 # Outputs: DO0, DO1, DO2, DO3
 # name               ID  w/b   ins   outs
-$__ABC_DPR16X4_COMB  2     0   8    4
+$__ABC9_DPR16X4_COMB  2     0   8    4
 
 #A0   A1   A2   A3   RAD0   RAD1   RAD2   RAD3
 0     0    0    0    141    379    275    379
diff --git a/techlibs/ecp5/abc_5g.lut b/techlibs/ecp5/abc9_5g.lut
similarity index 100%
rename from techlibs/ecp5/abc_5g.lut
rename to techlibs/ecp5/abc9_5g.lut
diff --git a/techlibs/ecp5/abc_5g_nowide.lut b/techlibs/ecp5/abc9_5g_nowide.lut
similarity index 100%
rename from techlibs/ecp5/abc_5g_nowide.lut
rename to techlibs/ecp5/abc9_5g_nowide.lut
diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc9_map.v
similarity index 89%
rename from techlibs/ecp5/abc_map.v
rename to techlibs/ecp5/abc9_map.v
index ffd25f06d..d8d70f9f6 100644
--- a/techlibs/ecp5/abc_map.v
+++ b/techlibs/ecp5/abc9_map.v
@@ -20,5 +20,5 @@ module TRELLIS_DPR16X4 (
       .RAD(RAD), .DO(\$DO )
     );
 
-    \$__ABC_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO));
+    \$__ABC9_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO));
 endmodule
diff --git a/techlibs/ecp5/abc9_model.v b/techlibs/ecp5/abc9_model.v
new file mode 100644
index 000000000..1dc8b5617
--- /dev/null
+++ b/techlibs/ecp5/abc9_model.v
@@ -0,0 +1,5 @@
+// ---------------------------------------
+
+(* abc9_box_id=2 *)
+module \$__ABC9_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+endmodule
diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc9_unmap.v
similarity index 52%
rename from techlibs/ecp5/abc_unmap.v
rename to techlibs/ecp5/abc9_unmap.v
index d43cdd93f..9ae143c46 100644
--- a/techlibs/ecp5/abc_unmap.v
+++ b/techlibs/ecp5/abc9_unmap.v
@@ -1,5 +1,5 @@
 // ---------------------------------------
 
-module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+module \$__ABC9_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
     assign Y = A;
 endmodule
diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v
deleted file mode 100644
index 56a733b75..000000000
--- a/techlibs/ecp5/abc_model.v
+++ /dev/null
@@ -1,5 +0,0 @@
-// ---------------------------------------
-
-(* abc_box_id=2 *)
-module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
-endmodule
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index db77dc127..f467218cc 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -9,19 +9,19 @@ module LUT4(input A, B, C, D, output Z);
 endmodule
 
 // ---------------------------------------
-(* abc_box_id=4, lib_whitebox *)
+(* abc9_box_id=4, lib_whitebox *)
 module L6MUX21 (input D0, D1, SD, output Z);
 	assign Z = SD ? D1 : D0;
 endmodule
 
 // ---------------------------------------
-(* abc_box_id=1, lib_whitebox *)
+(* abc9_box_id=1, lib_whitebox *)
 module CCU2C(
-	(* abc_carry *)
+	(* abc9_carry *)
 	input  CIN,
 	input  A0, B0, C0, D0, A1, B1, C1, D1,
 	output S0, S1,
-	(* abc_carry *)
+	(* abc9_carry *)
 	output COUT
 );
 	parameter [15:0] INIT0 = 16'h0000;
@@ -103,7 +103,7 @@ module TRELLIS_RAM16X2 (
 endmodule
 
 // ---------------------------------------
-(* abc_box_id=3, lib_whitebox *)
+(* abc9_box_id=3, lib_whitebox *)
 module PFUMX (input ALUT, BLUT, C0, output Z);
 	assign Z = C0 ? ALUT : BLUT;
 endmodule
@@ -115,7 +115,7 @@ module TRELLIS_DPR16X4 (
 	input        WRE,
 	input        WCK,
 	input  [3:0] RAD,
-	/* (* abc_arrival=<TODO> *) */
+	/* (* abc9_arrival=<TODO> *) */
 	output [3:0] DO
 );
 	parameter WCKMUX = "WCK";
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 67d2f483c..80aa1dbc5 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -307,16 +307,16 @@ struct SynthEcp5Pass : public ScriptPass
 			}
 			std::string techmap_args = "-map +/ecp5/latches_map.v";
 			if (abc9)
-				techmap_args += " -map +/ecp5/abc_map.v -max_iter 1";
+				techmap_args += " -map +/ecp5/abc9_map.v -max_iter 1";
 			run("techmap " + techmap_args);
 
 			if (abc9) {
-				run("read_verilog -icells -lib +/ecp5/abc_model.v");
+				run("read_verilog -icells -lib +/ecp5/abc9_model.v");
 				if (nowidelut)
-					run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
+					run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200");
 				else
-					run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
-				run("techmap -map +/ecp5/abc_unmap.v");
+					run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200");
+				run("techmap -map +/ecp5/abc9_unmap.v");
 			} else {
 				if (nowidelut)
 					run("abc -lut 4 -dress");
diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 0fbca9034..3c33fcb06 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,13 +28,13 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_model.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.lut))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_u.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_u.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_model.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_hx.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_hx.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_lp.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_lp.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_u.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_u.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc9_hx.box
similarity index 100%
rename from techlibs/ice40/abc_hx.box
rename to techlibs/ice40/abc9_hx.box
diff --git a/techlibs/ice40/abc_hx.lut b/techlibs/ice40/abc9_hx.lut
similarity index 100%
rename from techlibs/ice40/abc_hx.lut
rename to techlibs/ice40/abc9_hx.lut
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc9_lp.box
similarity index 100%
rename from techlibs/ice40/abc_lp.box
rename to techlibs/ice40/abc9_lp.box
diff --git a/techlibs/ice40/abc_lp.lut b/techlibs/ice40/abc9_lp.lut
similarity index 100%
rename from techlibs/ice40/abc_lp.lut
rename to techlibs/ice40/abc9_lp.lut
diff --git a/techlibs/ice40/abc_model.v b/techlibs/ice40/abc9_model.v
similarity index 79%
rename from techlibs/ice40/abc_model.v
rename to techlibs/ice40/abc9_model.v
index fe31b8811..26cf6cc22 100644
--- a/techlibs/ice40/abc_model.v
+++ b/techlibs/ice40/abc9_model.v
@@ -1,10 +1,10 @@
-(* abc_box_id = 1, lib_whitebox *)
+(* abc9_box_id = 1, lib_whitebox *)
 module \$__ICE40_CARRY_WRAPPER (
-	(* abc_carry *)
+	(* abc9_carry *)
 	output CO,
 	output O,
 	input A, B,
-	(* abc_carry *)
+	(* abc9_carry *)
 	input CI,
 	input I0, I3
 );
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc9_u.box
similarity index 100%
rename from techlibs/ice40/abc_u.box
rename to techlibs/ice40/abc9_u.box
diff --git a/techlibs/ice40/abc_u.lut b/techlibs/ice40/abc9_u.lut
similarity index 100%
rename from techlibs/ice40/abc_u.lut
rename to techlibs/ice40/abc9_u.lut
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 16a893226..f9e79a61d 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -2,9 +2,9 @@
 `define SB_DFF_REG reg Q = 0
 // `define SB_DFF_REG reg Q
 
-`define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
-`define ABC_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc_arrival=TIME *) `endif
-`define ABC_ARRIVAL_U(TIME)  `ifdef ICE40_U (* abc_arrival=TIME *) `endif
+`define ABC9_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc9_arrival=TIME *) `endif
+`define ABC9_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc9_arrival=TIME *) `endif
+`define ABC9_ARRIVAL_U(TIME)  `ifdef ICE40_U (* abc9_arrival=TIME *) `endif
 
 // SiliconBlue IO Cells
 
@@ -152,9 +152,9 @@ endmodule
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -163,9 +163,9 @@ module SB_DFF (
 endmodule
 
 module SB_DFFE (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -175,9 +175,9 @@ module SB_DFFE (
 endmodule
 
 module SB_DFFSR (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -189,9 +189,9 @@ module SB_DFFSR (
 endmodule
 
 module SB_DFFR (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -203,9 +203,9 @@ module SB_DFFR (
 endmodule
 
 module SB_DFFSS (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -217,9 +217,9 @@ module SB_DFFSS (
 endmodule
 
 module SB_DFFS (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -231,9 +231,9 @@ module SB_DFFS (
 endmodule
 
 module SB_DFFESR (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -247,9 +247,9 @@ module SB_DFFESR (
 endmodule
 
 module SB_DFFER (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -261,9 +261,9 @@ module SB_DFFER (
 endmodule
 
 module SB_DFFESS (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -277,9 +277,9 @@ module SB_DFFESS (
 endmodule
 
 module SB_DFFES (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -293,9 +293,9 @@ endmodule
 // Negative Edge SiliconBlue FF Cells
 
 module SB_DFFN (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -304,9 +304,9 @@ module SB_DFFN (
 endmodule
 
 module SB_DFFNE (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -316,9 +316,9 @@ module SB_DFFNE (
 endmodule
 
 module SB_DFFNSR (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -330,9 +330,9 @@ module SB_DFFNSR (
 endmodule
 
 module SB_DFFNR (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -344,9 +344,9 @@ module SB_DFFNR (
 endmodule
 
 module SB_DFFNSS (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -358,9 +358,9 @@ module SB_DFFNSS (
 endmodule
 
 module SB_DFFNS (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -372,9 +372,9 @@ module SB_DFFNS (
 endmodule
 
 module SB_DFFNESR (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -388,9 +388,9 @@ module SB_DFFNESR (
 endmodule
 
 module SB_DFFNER (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -402,9 +402,9 @@ module SB_DFFNER (
 endmodule
 
 module SB_DFFNESS (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -418,9 +418,9 @@ module SB_DFFNESS (
 endmodule
 
 module SB_DFFNES (
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -434,9 +434,9 @@ endmodule
 // SiliconBlue RAM Cells
 
 module SB_RAM40_4K (
-	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
-	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
-	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
+	`ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC9_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -605,9 +605,9 @@ module SB_RAM40_4K (
 endmodule
 
 module SB_RAM40_4KNR (
-	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
-	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
-	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
+	`ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC9_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -673,9 +673,9 @@ module SB_RAM40_4KNR (
 endmodule
 
 module SB_RAM40_4KNW (
-	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
-	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
-	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
+	`ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC9_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -741,9 +741,9 @@ module SB_RAM40_4KNW (
 endmodule
 
 module SB_RAM40_4KNRNW (
-	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
-	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
-	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
+	`ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC9_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -813,9 +813,9 @@ endmodule
 module ICESTORM_LC (
 	input I0, I1, I2, I3, CIN, CLK, CEN, SR,
 	output LO,
-	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(796)
-	`ABC_ARRIVAL_U(1391)
+	`ABC9_ARRIVAL_HX(540)
+	`ABC9_ARRIVAL_LP(796)
+	`ABC9_ARRIVAL_U(1391)
 	output O,
 	output COUT
 );
@@ -1417,7 +1417,6 @@ module SB_MAC16 (
 	input ADDSUBTOP, ADDSUBBOT,
 	input OHOLDTOP, OHOLDBOT,
 	input CI, ACCUMCI, SIGNEXTIN,
-	//`ABC_ARRIVAL_U(1984)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [31:0] O,
 	output CO, ACCUMCO, SIGNEXTOUT
 );
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2e4684c19..b66c6bf57 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -349,7 +349,7 @@ struct SynthIce40Pass : public ScriptPass
 			}
 			if (!noabc) {
 				if (abc == "abc9") {
-					run("read_verilog -icells -lib +/ice40/abc_model.v");
+					run("read_verilog -icells -lib +/ice40/abc9_model.v");
 					int wire_delay;
 					if (device_opt == "lp")
 						wire_delay = 400;
@@ -357,7 +357,7 @@ struct SynthIce40Pass : public ScriptPass
 						wire_delay = 750;
 					else
 						wire_delay = 250;
-					run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+					run(abc + stringf(" -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
 				}
 				else
 					run(abc + " -dress -lut 4", "(skip if -noabc)");
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index ae82311a9..0ae67d9e7 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -44,12 +44,12 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/dsp_map.v))
 
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_map.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_unmap.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_model.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7_nowide.lut))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_unmap.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_model.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_xc7.box))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_xc7.lut))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_xc7_nowide.lut))
 
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc9_map.v
similarity index 88%
rename from techlibs/xilinx/abc_map.v
rename to techlibs/xilinx/abc9_map.v
index e4976092c..0eac08f3f 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -39,8 +39,8 @@ module RAM32X1D (
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
     .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
   );
-  \$__ABC_LUT6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
-  \$__ABC_LUT6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
+  \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
+  \$__ABC9_LUT6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
 endmodule
 
 module RAM64X1D (
@@ -62,8 +62,8 @@ module RAM64X1D (
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
     .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
   );
-  \$__ABC_LUT6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
-  \$__ABC_LUT6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
+  \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
+  \$__ABC9_LUT6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
 endmodule
 
 module RAM128X1D (
@@ -84,8 +84,8 @@ module RAM128X1D (
     .A(A),
     .DPRA(DPRA)
   );
-  \$__ABC_LUT7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
-  \$__ABC_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO));
+  \$__ABC9_LUT7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
+  \$__ABC9_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO));
 endmodule
 
 module SRL16E (
@@ -101,7 +101,7 @@ module SRL16E (
     .Q(\$Q ),
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
   );
-  \$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A0, A1, A2, A3, 1'b1}), .Y(Q));
+  \$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A0, A1, A2, A3, 1'b1}), .Y(Q));
 endmodule
 
 module SRLC32E (
@@ -119,7 +119,7 @@ module SRLC32E (
     .Q(\$Q ), .Q31(Q31),
     .A(A), .CE(CE), .CLK(CLK), .D(D)
   );
-  \$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q));
+  \$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q));
 endmodule
 
 module DSP48E1 (
@@ -308,15 +308,15 @@ __CELL__ #(
         if (AREG == 0 && MREG == 0 && PREG == 0)
             assign iA = A, pA = 1'bx;
         else
-            \$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
+            \$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
         if (BREG == 0 && MREG == 0 && PREG == 0)
             assign iB = B, pB = 1'bx;
         else
-            \$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
+            \$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
         if (CREG == 0 && PREG == 0)
             assign iC = C, pC = 1'bx;
         else
-            \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
+            \$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
         if (DREG == 0)
             assign iD = D;
         else if (techmap_guard)
@@ -327,27 +327,27 @@ __CELL__ #(
         assign pAD = 1'bx;
     if (PREG == 0) begin
         if (MREG == 1)
-        \$__ABC_REG rM (.Q(pM));
+        \$__ABC9_REG rM (.Q(pM));
         else
         assign pM = 1'bx;
         assign pP = 1'bx;
     end else begin
             assign pM = 1'bx;
-            \$__ABC_REG rP (.Q(pP));
+            \$__ABC9_REG rP (.Q(pP));
         end
 
         if (MREG == 0 && PREG == 0)
             assign mP = oP, mPCOUT = oPCOUT;
         else
             assign mP = 1'bx, mPCOUT = 1'bx;
-        \$__ABC_DSP48E1_MULT_P_MUX muxP (
+        \$__ABC9_DSP48E1_MULT_P_MUX muxP (
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
         );
-        \$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
+        \$__ABC9_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
         );
 
-        `DSP48E1_INST(\$__ABC_DSP48E1_MULT )
+        `DSP48E1_INST(\$__ABC9_DSP48E1_MULT )
     end
     else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
         // Disconnect the A-input if MREG is enabled, since
@@ -355,26 +355,26 @@ __CELL__ #(
         if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0)
             assign iA = A, pA = 1'bx;
         else
-            \$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
+            \$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
         if (BREG == 0 && MREG == 0 && PREG == 0)
             assign iB = B, pB = 1'bx;
         else
-            \$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
+            \$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
         if (CREG == 0 && PREG == 0)
             assign iC = C, pC = 1'bx;
         else
-            \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
+            \$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
         if (DREG == 0 && ADREG == 0)
             assign iD = D, pD = 1'bx;
         else
-            \$__ABC_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD));
+            \$__ABC9_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD));
         if (PREG == 0) begin
             if (MREG == 1) begin
                 assign pAD = 1'bx;
-        \$__ABC_REG rM (.Q(pM));
+        \$__ABC9_REG rM (.Q(pM));
             end else begin
                 if (ADREG == 1)
-                    \$__ABC_REG rAD (.Q(pAD));
+                    \$__ABC9_REG rAD (.Q(pAD));
                 else
                     assign pAD = 1'bx;
         assign pM = 1'bx;
@@ -382,21 +382,21 @@ __CELL__ #(
         assign pP = 1'bx;
     end else begin
             assign pAD = 1'bx, pM = 1'bx;
-            \$__ABC_REG rP (.Q(pP));
+            \$__ABC9_REG rP (.Q(pP));
         end
 
         if (MREG == 0 && PREG == 0)
             assign mP = oP, mPCOUT = oPCOUT;
         else
             assign mP = 1'bx, mPCOUT = 1'bx;
-        \$__ABC_DSP48E1_MULT_DPORT_P_MUX muxP (
+        \$__ABC9_DSP48E1_MULT_DPORT_P_MUX muxP (
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
         );
-        \$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT (
+        \$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT (
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
         );
 
-        `DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT )
+        `DSP48E1_INST(\$__ABC9_DSP48E1_MULT_DPORT )
     end
     else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
         // Disconnect the A-input if MREG is enabled, since
@@ -404,15 +404,15 @@ __CELL__ #(
         if (AREG == 0 && PREG == 0)
             assign iA = A, pA = 1'bx;
         else
-            \$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
+            \$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
         if (BREG == 0 && PREG == 0)
             assign iB = B, pB = 1'bx;
         else
-            \$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
+            \$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
         if (CREG == 0 && PREG == 0)
             assign iC = C, pC = 1'bx;
         else
-            \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
+            \$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
         if (DREG == 1 && techmap_guard)
             $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
         assign pD = 1'bx;
@@ -423,7 +423,7 @@ __CELL__ #(
             $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
         assign pM = 1'bx;
         if (PREG == 1)
-            \$__ABC_REG rP (.Q(pP));
+            \$__ABC9_REG rP (.Q(pP));
         else
             assign pP = 1'bx;
 
@@ -431,14 +431,14 @@ __CELL__ #(
             assign mP = oP, mPCOUT = oPCOUT;
         else
             assign mP = 1'bx, mPCOUT = 1'bx;
-        \$__ABC_DSP48E1_P_MUX muxP (
+        \$__ABC9_DSP48E1_P_MUX muxP (
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
         );
-        \$__ABC_DSP48E1_PCOUT_MUX muxPCOUT (
+        \$__ABC9_DSP48E1_PCOUT_MUX muxPCOUT (
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
         );
 
-        `DSP48E1_INST(\$__ABC_DSP48E1 )
+        `DSP48E1_INST(\$__ABC9_DSP48E1 )
     end
     else
         $error("Invalid DSP48E1 configuration");
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc9_model.v
similarity index 83%
rename from techlibs/xilinx/abc_model.v
rename to techlibs/xilinx/abc9_model.v
index f19235a27..8c8e1556c 100644
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -24,7 +24,7 @@
 //   Necessary to make these an atomic unit so that
 //   ABC cannot optimise just one of the MUXF7 away
 //   and expect to save on its delay
-(* abc_box_id = 3, lib_whitebox *)
+(* abc9_box_id = 3, lib_whitebox *)
 module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
   assign O = S1 ? (S0 ? I3 : I2)
                 : (S0 ? I1 : I0);
@@ -36,32 +36,32 @@ endmodule
 //   is only committed on the next clock edge).
 //   To model the combinatorial path, such cells have to be split
 //   into comb and seq parts, with this box modelling only the former.
-(* abc_box_id=2000 *)
-module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
+(* abc9_box_id=2000 *)
+module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
 endmodule
 // Box to emulate comb/seq behaviour of RAMD128
-(* abc_box_id=2001 *)
-module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
+(* abc9_box_id=2001 *)
+module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
 endmodule
 
 
 // Modules used to model the comb/seq behaviour of DSP48E1
-//   With abc_map.v responsible for splicing the below modules
+//   With abc9_map.v responsible for splicing the below modules
 //   between the combinatorial DSP48E1 box (e.g. disconnecting
 //   A when AREG, MREG or PREG is enabled and splicing in the
-//   "$__ABC_DSP48E1_REG" blackbox as "REG" in the diagram below)
+//   "$__ABC9_DSP48E1_REG" blackbox as "REG" in the diagram below)
 //   this acts to first disables the combinatorial path (as there
 //   is no connectivity through REG), and secondly, since this is
 //   blackbox a new PI will be introduced with an arrival time of
 //   zero.
-//   Note: Since these "$__ABC_DSP48E1_REG" modules are of a
+//   Note: Since these "$__ABC9_DSP48E1_REG" modules are of a
 //   sequential nature, they are not passed as a box to ABC and
 //   (desirably) represented as PO/PIs.
 //
 //   At the DSP output, we place a blackbox mux ("M" in the diagram
 //   below) to capture the fact that the critical-path could come
 //   from any one of its inputs.
-//   In contrast to "REG", the "$__ABC_DSP48E1_*_MUX" modules are
+//   In contrast to "REG", the "$__ABC9_DSP48E1_*_MUX" modules are
 //   combinatorial blackboxes that do get passed to ABC.
 //   The propagation delay through this box (specified in the box
 //   file) captures the arrival time of the register (i.e.
@@ -90,18 +90,18 @@ endmodule
 //    B >>------|         |
 //              +---------+
 //
-`define ABC_DSP48E1_MUX(__NAME__) """
+`define ABC9_DSP48E1_MUX(__NAME__) """
 module __NAME__ (input Aq, ADq, Bq, Cq, Dq, input [47:0] I, input Mq, input [47:0] P, input Pq, output [47:0] O);
 endmodule
 """
-(* abc_box_id=2100 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_P_MUX )
-(* abc_box_id=2101 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_PCOUT_MUX )
-(* abc_box_id=2102 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_P_MUX )
-(* abc_box_id=2103 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX )
-(* abc_box_id=2104 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_P_MUX )
-(* abc_box_id=2105 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_PCOUT_MUX )
+(* abc9_box_id=2100 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_P_MUX )
+(* abc9_box_id=2101 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_PCOUT_MUX )
+(* abc9_box_id=2102 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_DPORT_P_MUX )
+(* abc9_box_id=2103 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX )
+(* abc9_box_id=2104 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_P_MUX )
+(* abc9_box_id=2105 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_PCOUT_MUX )
 
-`define ABC_DSP48E1(__NAME__) """
+`define ABC9_DSP48E1(__NAME__) """
 module __NAME__ (
     output [29:0] ACOUT,
     output [17:0] BCOUT,
@@ -185,6 +185,6 @@ module __NAME__ (
     parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
 endmodule
 """
-(* abc_box_id=3000 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT )
-(* abc_box_id=3001 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT_DPORT )
-(* abc_box_id=3002 *) `ABC_DSP48E1(\$__ABC_DSP48E1 )
+(* abc9_box_id=3000 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1_MULT )
+(* abc9_box_id=3001 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1_MULT_DPORT )
+(* abc9_box_id=3002 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1 )
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc9_unmap.v
similarity index 92%
rename from techlibs/xilinx/abc_unmap.v
rename to techlibs/xilinx/abc9_unmap.v
index 8bd0579ed..ad6469702 100644
--- a/techlibs/xilinx/abc_unmap.v
+++ b/techlibs/xilinx/abc9_unmap.v
@@ -20,19 +20,19 @@
 
 // ============================================================================
 
-module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
+module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
   assign Y = A;
 endmodule
-module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
+module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
   assign Y = A;
 endmodule
 
-module \$__ABC_REG (input [WIDTH-1:0] I, output [WIDTH-1:0] O, output Q);
+module \$__ABC9_REG (input [WIDTH-1:0] I, output [WIDTH-1:0] O, output Q);
   parameter WIDTH = 1;
   assign O = I;
 endmodule
-(* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC_DSP48E1_P_MUX $__ABC_DSP48E1_PCOUT_MUX" *)
-module \$__ABC_DSP48E1_MUX (
+(* techmap_celltype = "$__ABC9_DSP48E1_MULT_P_MUX $__ABC9_DSP48E1_MULT_PCOUT_MUX $__ABC9_DSP48E1_MULT_DPORT_P_MUX $__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC9_DSP48E1_P_MUX $__ABC9_DSP48E1_PCOUT_MUX" *)
+module \$__ABC9_DSP48E1_MUX (
   input Aq, Bq, Cq, Dq, ADq,
   input [47:0] I,
   input Mq,
@@ -43,8 +43,8 @@ module \$__ABC_DSP48E1_MUX (
   assign O = I;
 endmodule
 
-(* techmap_celltype = "$__ABC_DSP48E1_MULT $__ABC_DSP48E1_MULT_DPORT $__ABC_DSP48E1" *)
-module \$__ABC_DSP48E1 (
+(* techmap_celltype = "$__ABC9_DSP48E1_MULT $__ABC9_DSP48E1_MULT_DPORT $__ABC9_DSP48E1" *)
+module \$__ABC9_DSP48E1 (
     (* techmap_autopurge *) output [29:0] ACOUT,
     (* techmap_autopurge *) output [17:0] BCOUT,
     (* techmap_autopurge *) output reg CARRYCASCOUT,
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc9_xc7.box
similarity index 99%
rename from techlibs/xilinx/abc_xc7.box
rename to techlibs/xilinx/abc9_xc7.box
index 3da3d1b3f..774388d49 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc9_xc7.box
@@ -50,18 +50,18 @@ CARRY4 4 1 10 8
 #   into comb and seq parts, with this box modelling only the former.
 # Inputs: A S0 S1 S2 S3 S4 S5
 # Outputs: Y
-$__ABC_LUT6 2000 0 7 1
+$__ABC9_LUT6 2000 0 7 1
 0 642 631 472 407 238 127
 
 # SLICEM/A6LUT + F7BMUX
 # Box to emulate comb/seq behaviour of RAMD128
 # Inputs: A S0 S1 S2 S3 S4 S5 S6
 # Outputs: DPO SPO
-$__ABC_LUT7 2001 0 8 1
+$__ABC9_LUT7 2001 0 8 1
 0 1047 1036 877 812 643 532 478
 
 # Boxes used to represent the comb/seq behaviour of DSP48E1
-#   With abc_map.v responsible for disconnecting inputs to
+#   With abc9_map.v responsible for disconnecting inputs to
 #   the combinatorial DSP48E1 model by a register (e.g.
 #   disconnecting A when AREG, MREG or PREG is enabled)
 #   this mux captures the existence of a replacement path
@@ -70,7 +70,7 @@ $__ABC_LUT7 2001 0 8 1
 #   the mux at zero time, the combinatorial delay through
 #   these muxes thus represents the clock-to-q delay at
 #   P/PCOUT.
-$__ABC_DSP48E1_MULT_P_MUX 2100 0 103 48
+$__ABC9_DSP48E1_MULT_P_MUX 2100 0 103 48
 # A AD    B    C D                                                                                               I    M P                                                                                                Pq
 2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
 2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
@@ -120,7 +120,7 @@ $__ABC_DSP48E1_MULT_P_MUX 2100 0 103 48
 2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
 2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
 2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-$__ABC_DSP48E1_MULT_PCOUT_MUX 2101 0 103 48
+$__ABC9_DSP48E1_MULT_PCOUT_MUX 2101 0 103 48
 # A AD    B    C D                                                                                               I   M P                                                                                                Pq
 3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
 3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
@@ -170,7 +170,7 @@ $__ABC_DSP48E1_MULT_PCOUT_MUX 2101 0 103 48
 3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
 3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
 3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
-$__ABC_DSP48E1_MULT_DPORT_P_MUX 2102 0 103 48
+$__ABC9_DSP48E1_MULT_DPORT_P_MUX 2102 0 103 48
 # A    AD    B    C    D                                                                                               I    M P                                                                                                Pq
 3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
 3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
@@ -220,7 +220,7 @@ $__ABC_DSP48E1_MULT_DPORT_P_MUX 2102 0 103 48
 3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
 3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
 3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX 2103 0 103 48
+$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX 2103 0 103 48
 # A    AD    B    C    D                                                                                               I    M P                                                                                                Pq
 4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
 4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
@@ -270,7 +270,7 @@ $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX 2103 0 103 48
 4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
 4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
 4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
-$__ABC_DSP48E1_P_MUX 2104 0 103 48
+$__ABC9_DSP48E1_P_MUX 2104 0 103 48
 # A AD    B    C D                                                                                               I M P                                                                                                Pq
 1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
 1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
@@ -320,7 +320,7 @@ $__ABC_DSP48E1_P_MUX 2104 0 103 48
 1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
 1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
 1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-$__ABC_DSP48E1_PCOUT_MUX 2105 0 103 48
+$__ABC9_DSP48E1_PCOUT_MUX 2105 0 103 48
 # A AD    B    C D                                                                                               I    M P                                                                                                Pq
 1780 - 1765 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
 1780 - 1765 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
@@ -371,7 +371,7 @@ $__ABC_DSP48E1_PCOUT_MUX 2105 0 103 48
 1780 - 1765 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
 1780 - 1765 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435
 
-$__ABC_DSP48E1_MULT 3000 0 263 154
+$__ABC9_DSP48E1_MULT 3000 0 263 154
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 - - 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 -
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 - - 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 -
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 - - 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 -
@@ -635,7 +635,7 @@ $__ABC_DSP48E1_MULT 3000 0 263 154
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-$__ABC_DSP48E1_MULT_DPORT 3001 0 263 154
+$__ABC9_DSP48E1_MULT_DPORT 3001 0 263 154
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 - - 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 -
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 - - 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 -
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 - - 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 -
@@ -899,7 +899,7 @@ $__ABC_DSP48E1_MULT_DPORT 3001 0 263 154
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-$__ABC_DSP48E1 3002 0 263 154
+$__ABC9_DSP48E1 3002 0 263 154
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 - - 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 -
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 - - 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 -
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 - - 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 -
diff --git a/techlibs/xilinx/abc_xc7.lut b/techlibs/xilinx/abc9_xc7.lut
similarity index 100%
rename from techlibs/xilinx/abc_xc7.lut
rename to techlibs/xilinx/abc9_xc7.lut
diff --git a/techlibs/xilinx/abc_xc7_nowide.lut b/techlibs/xilinx/abc9_xc7_nowide.lut
similarity index 100%
rename from techlibs/xilinx/abc_xc7_nowide.lut
rename to techlibs/xilinx/abc9_xc7_nowide.lut
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 258999f18..28cd208cd 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -184,12 +184,12 @@ module MUXCY(output O, input CI, DI, S);
   assign O = S ? CI : DI;
 endmodule
 
-(* abc_box_id = 1, lib_whitebox *)
+(* abc9_box_id = 1, lib_whitebox *)
 module MUXF7(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
 
-(* abc_box_id = 2, lib_whitebox *)
+(* abc9_box_id = 2, lib_whitebox *)
 module MUXF8(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
@@ -198,12 +198,12 @@ module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
 
-(* abc_box_id = 4, lib_whitebox *)
+(* abc9_box_id = 4, lib_whitebox *)
 module CARRY4(
-  (* abc_carry *)
+  (* abc9_carry *)
   output [3:0] CO,
   output [3:0] O,
-  (* abc_carry *)
+  (* abc9_carry *)
   input        CI,
   input        CYINIT,
   input  [3:0] DI, S
@@ -241,7 +241,7 @@ endmodule
 // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
 
 module FDRE (
-  (* abc_arrival=303 *)
+  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_C_INVERTED" *)
@@ -264,7 +264,7 @@ module FDRE (
 endmodule
 
 module FDSE (
-  (* abc_arrival=303 *)
+  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_C_INVERTED" *)
@@ -287,7 +287,7 @@ module FDSE (
 endmodule
 
 module FDCE (
-  (* abc_arrival=303 *)
+  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_C_INVERTED" *)
@@ -312,7 +312,7 @@ module FDCE (
 endmodule
 
 module FDPE (
-  (* abc_arrival=303 *)
+  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_C_INVERTED" *)
@@ -337,7 +337,7 @@ module FDPE (
 endmodule
 
 module FDRE_1 (
-  (* abc_arrival=303 *)
+  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   input C,
@@ -349,7 +349,7 @@ module FDRE_1 (
 endmodule
 
 module FDSE_1 (
-  (* abc_arrival=303 *)
+  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   input C,
@@ -361,7 +361,7 @@ module FDSE_1 (
 endmodule
 
 module FDCE_1 (
-  (* abc_arrival=303 *)
+  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   input C,
@@ -373,7 +373,7 @@ module FDCE_1 (
 endmodule
 
 module FDPE_1 (
-  (* abc_arrival=303 *)
+  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   input C,
@@ -430,7 +430,7 @@ endmodule
 
 module RAM32X1D (
   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-  (* abc_arrival=1153 *)
+  (* abc9_arrival=1153 *)
   output DPO, SPO,
   input  D,
   (* clkbuf_sink *)
@@ -453,7 +453,7 @@ endmodule
 
 module RAM64X1D (
   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-  (* abc_arrival=1153 *)
+  (* abc9_arrival=1153 *)
   output DPO, SPO,
   input  D,
   (* clkbuf_sink *)
@@ -476,7 +476,7 @@ endmodule
 
 module RAM128X1D (
   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-  (* abc_arrival=1153 *)
+  (* abc9_arrival=1153 *)
   output DPO, SPO,
   input        D,
   (* clkbuf_sink *)
@@ -496,7 +496,7 @@ endmodule
 
 module SRL16E (
   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
-  (* abc_arrival=1472 *)
+  (* abc9_arrival=1472 *)
   output Q,
   input A0, A1, A2, A3, CE,
   (* clkbuf_sink *)
@@ -544,9 +544,9 @@ endmodule
 
 module SRLC32E (
   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
-  (* abc_arrival=1472 *)
+  (* abc9_arrival=1472 *)
   output Q,
-  (* abc_arrival=1114 *)
+  (* abc9_arrival=1114 *)
   output Q31,
   input [4:0] A,
   input CE,
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 7085214de..5c2b1402c 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -474,13 +474,14 @@ struct SynthXilinxPass : public ScriptPass
 				run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut'; option for '-retime')");
 			else if (abc9) {
 				if (family != "xc7")
-					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
-				run("techmap -map +/xilinx/abc_map.v -max_iter 1");
-				run("read_verilog -icells -lib +/xilinx/abc_model.v");
+					log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
+                            "will use timing for 'xc7' instead.\n", family.c_str());
+				run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
+				run("read_verilog -icells -lib +/xilinx/abc9_model.v");
 				if (nowidelut)
-					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
+					run("abc9 -lut +/xilinx/abc9_xc7_nowide.lut -box +/xilinx/abc9_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 				else
-					run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
+					run("abc9 -lut +/xilinx/abc9_xc7.lut -box +/xilinx/abc9_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 			}
 			else {
 				if (nowidelut)
@@ -498,7 +499,7 @@ struct SynthXilinxPass : public ScriptPass
 			if (help_mode)
 				techmap_args += " [-map " + ff_map_file + "]";
 			else if (abc9)
-				techmap_args += " -map +/xilinx/abc_unmap.v";
+				techmap_args += " -map +/xilinx/abc9_unmap.v";
 			else
 				techmap_args += " -map " + ff_map_file;
 			run("techmap " + techmap_args);
diff --git a/techlibs/xilinx/xc6s_brams_bb.v b/techlibs/xilinx/xc6s_brams_bb.v
index 041d6b54f..3c323a90b 100644
--- a/techlibs/xilinx/xc6s_brams_bb.v
+++ b/techlibs/xilinx/xc6s_brams_bb.v
@@ -19,9 +19,13 @@ module RAMB8BWER (
 	input [1:0] WEAWEL,
 	input [1:0] WEBWEU,
 
+	/* (* abc9_arrival=<TODO> *) */
 	output [15:0] DOADO,
+	/* (* abc9_arrival=<TODO> *) */
 	output [15:0] DOBDO,
+	/* (* abc9_arrival=<TODO> *) */
 	output [1:0] DOPADOP,
+	/* (* abc9_arrival=<TODO> *) */
 	output [1:0] DOPBDOP
 );
 	parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@@ -109,9 +113,13 @@ module RAMB16BWER (
 	input [3:0] WEA,
 	input [3:0] WEB,
 
+	/* (* abc9_arrival=<TODO> *) */
 	output [31:0] DOA,
+	/* (* abc9_arrival=<TODO> *) */
 	output [31:0] DOB,
+	/* (* abc9_arrival=<TODO> *) */
 	output [3:0] DOPA,
+	/* (* abc9_arrival=<TODO> *) */
 	output [3:0] DOPB
 );
 	parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v
index a28ba5b14..c374f26b9 100644
--- a/techlibs/xilinx/xc7_brams_bb.v
+++ b/techlibs/xilinx/xc7_brams_bb.v
@@ -31,13 +31,13 @@ module RAMB18E1 (
 	input [1:0] WEA,
 	input [3:0] WEBWE,
 
-	(* abc_arrival=2454 *)
+	(* abc9_arrival=2454 *)
 	output [15:0] DOADO,
-	(* abc_arrival=2454 *)
+	(* abc9_arrival=2454 *)
 	output [15:0] DOBDO,
-	(* abc_arrival=2454 *)
+	(* abc9_arrival=2454 *)
 	output [1:0] DOPADOP,
-	(* abc_arrival=2454 *)
+	(* abc9_arrival=2454 *)
 	output [1:0] DOPBDOP
 );
 	parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@@ -169,13 +169,13 @@ module RAMB36E1 (
 	input [3:0] WEA,
 	input [7:0] WEBWE,
 
-	(* abc_arrival=2454 *)
+	(* abc9_arrival=2454 *)
 	output [31:0] DOADO,
-	(* abc_arrival=2454 *)
+	(* abc9_arrival=2454 *)
 	output [31:0] DOBDO,
-	(* abc_arrival=2454 *)
+	(* abc9_arrival=2454 *)
 	output [3:0] DOPADOP,
-	(* abc_arrival=2454 *)
+	(* abc9_arrival=2454 *)
 	output [3:0] DOPBDOP
 );
 	parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;