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abc9: generate $abc9_holes design instead of <name>$holes

This commit is contained in:
Eddie Hung 2020-04-15 16:13:57 -07:00
parent c52bb11fb6
commit ec4bbb1444
3 changed files with 28 additions and 18 deletions
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12
backends/aiger/xaiger.cc
View File

@ -676,7 +676,13 @@ struct XAigerWriter
f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
f.write(buffer_str.data(), buffer_str.size());
RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
RTLIL::Design *holes_design;
auto it = saved_designs.find("$abc9_holes");
if (it != saved_designs.end())
holes_design = it->second;
else
holes_design = nullptr;
RTLIL::Module *holes_module = holes_design ? holes_design->module(module->name) : nullptr;
if (holes_module) {
std::stringstream a_buffer;
XAigerWriter writer(holes_module, false /* dff_mode */, true /* holes_mode */);
@ -768,8 +774,8 @@ struct XAigerBackend : public Backend {
log("Write the top module (according to the (* top *) attribute or if only one module\n");
log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, (optionally\n");
log("$_DFF_N_, $_DFF_P_), or non (* abc9_box *) cells will be converted into psuedo-\n");
log("inputs and pseudo-outputs. Whitebox contents will be taken from the\n");
log("'<module-name>$holes' module, if it exists.\n");
log("inputs and pseudo-outputs. Whitebox contents will be taken from the equivalent\n");
log("module in the '$abc9_holes' design, if it exists.\n");
log("\n");
log(" -ascii\n");
log(" write ASCII version of AIGER format\n");

18
passes/techmap/abc9.cc
View File

@ -345,15 +345,18 @@ struct Abc9Pass : public ScriptPass
else if (box_file.empty()) {
run("abc9_ops -prep_box");
}
run("select -set abc9_holes A:abc9_holes");
run("flatten -wb @abc9_holes");
run("techmap @abc9_holes");
run("opt -purge @abc9_holes");
run("design -stash $abc9");
run("design -load $abc9_holes");
run("techmap -wb -map %$abc9 -map +/techmap.v");
run("opt -purge");
run("aigmap");
run("wbflip @abc9_holes");
run("wbflip");
run("design -stash $abc9_holes");
run("design -load $abc9");
}
if (check_label("map")) {
run("aigmap");
if (help_mode) {
run("foreach module in selection");
run(" abc9_ops -write_lut <abc-temp-dir>/input.lut", "(skip if '-lut' or '-luts')");
@ -372,7 +375,6 @@ struct Abc9Pass : public ScriptPass
log("Skipping module %s as it contains processes.\n", log_id(mod));
continue;
}
log_assert(!mod->attributes.count(ID::abc9_box_id));
log_push();
active_design->selection().select(mod);
@ -432,8 +434,10 @@ struct Abc9Pass : public ScriptPass
if (dff_mode || help_mode) {
run("techmap -wb -map %$abc9_unmap", "(only if -dff)"); // techmap user design from submod back to original cell
// ($_DFF_[NP]_ already shorted by -reintegrate)
run("design -delete $abc9_unmap");
run("design -delete $abc9_unmap", " (only if -dff)");
}
if (saved_designs.count("$abc9_holes") || help_mode)
run("design -delete $abc9_holes");
}
}
} Abc9Pass;

16
passes/techmap/abc9_ops.cc
View File

@ -368,9 +368,13 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
log_assert(no_loops);
RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
auto r = saved_designs.emplace("$abc9_holes", nullptr);
if (r.second)
r.first->second = new Design;
RTLIL::Design *holes_design = r.first->second;
log_assert(holes_design);
RTLIL::Module *holes_module = holes_design->addModule(module->name);
log_assert(holes_module);
holes_module->set_bool_attribute(ID::abc9_holes);
dict<IdString, Cell*> cell_cache;
TimingInfo timing;
@ -1246,9 +1250,8 @@ struct Abc9OpsPass : public Pass {
log("\n");
log(" -prep_xaiger\n");
log(" prepare the design for XAIGER output. this includes computing the\n");
log(" topological ordering of ABC9 boxes, as well as preparing the\n");
log(" '<module-name>$holes' module that contains the logic behaviour of ABC9\n");
log(" whiteboxes.\n");
log(" topological ordering of ABC9 boxes, as well as preparing the '$abc9_holes'\n");
log(" design that contains the logic behaviour of ABC9 whiteboxes.\n");
log("\n");
log(" -dff\n");
log(" consider flop cells (those instantiating modules marked with (* abc9_flop *))\n");
@ -1388,9 +1391,6 @@ struct Abc9OpsPass : public Pass {
prep_box(design);
for (auto mod : design->selected_modules()) {
if (mod->get_bool_attribute(ID::abc9_holes))
continue;
if (mod->processes.size() > 0) {
log("Skipping module %s as it contains processes.\n", log_id(mod));
continue;