mirror of https://github.com/YosysHQ/yosys.git
opt_expr: Sx to Sz; spotted by @Xiretza
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@ -175,7 +175,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
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}
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}
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bool def = (bit_a != State::Sx && bit_a != State::Sz && bit_b != State::Sx && bit_b != State::Sx);
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bool def = (bit_a != State::Sx && bit_a != State::Sz && bit_b != State::Sx && bit_b != State::Sz);
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if (def || !keepdc) {
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if (bit_a.wire == NULL && bit_b.wire == NULL)
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group_idx = GRP_CONST_AB;
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