mirror of https://github.com/YosysHQ/yosys.git
Fix multiple driver issue
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449b1d2c6f
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ac5b5e97bc
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@ -228,11 +228,16 @@ struct SubmodWorker
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RTLIL::SigSpec old_sig = sigmap(it.first);
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RTLIL::Wire *new_wire = it.second.new_wire;
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if (new_wire->port_id > 0) {
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// Prevents "ERROR: Mismatch in directionality ..." when flattening
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if (new_wire->port_output)
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for (auto &b : old_sig)
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for (int i = 0; i < GetSize(old_sig); i++) {
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auto &b = old_sig[i];
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// Prevents "ERROR: Mismatch in directionality ..." when flattening
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if (!b.wire)
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b = module->addWire(NEW_ID);
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// Prevents "Warning: multiple conflicting drivers ..."
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else if (!it.second.is_int_driven[i])
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b = module->addWire(NEW_ID);
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}
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new_cell->setPort(new_wire->name, old_sig);
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}
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}
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