riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

abc9_ops: -prep_dff_map to check $_DFF_[NP]_.Q drives module output

This commit is contained in:
Eddie Hung 2020-04-14 12:35:12 -07:00
parent 489e83fc1e
commit 8bad885e78
1 changed files with 5 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
passes/techmap/abc9_ops.cc
View File

@ -175,6 +175,10 @@ void prep_dff_map(RTLIL::Design *design)
// because ABC9 doesn't support them
Q = cell->getPort(ID::Q);
log_assert(GetSize(Q.wire) == 1);
if (!Q.wire->port_output)
log_error("Module '%s' contains a %s cell where its 'Q' port does not drive a module output!\n", log_id(module), log_id(cell->type));
Const init = Q.wire->attributes.at(ID::init, State::Sx);
log_assert(GetSize(init) == 1);
if (init != State::S0) {
@ -1207,7 +1211,7 @@ struct Abc9OpsPass : public Pass {
log(" -prep_dff_unmap\n");
log(" fill in previously created '$abc9_unmap' design to contain techmap rules\n");
log(" for mapping *_$abc9_flop cells back into their original (* abc9_flop *)\n");
log(" cells(including their original parameters).\n");
log(" cells (including their original parameters).\n");
log("\n");
log(" -prep_delays\n");
log(" insert `$__ABC9_DELAY' blackbox cells into the design to account for\n");