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abc9_ops: -prep_dff_map to check $_DFF_[NP]_.Q drives module output
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@ -175,6 +175,10 @@ void prep_dff_map(RTLIL::Design *design)
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// because ABC9 doesn't support them
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Q = cell->getPort(ID::Q);
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log_assert(GetSize(Q.wire) == 1);
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if (!Q.wire->port_output)
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log_error("Module '%s' contains a %s cell where its 'Q' port does not drive a module output!\n", log_id(module), log_id(cell->type));
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Const init = Q.wire->attributes.at(ID::init, State::Sx);
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log_assert(GetSize(init) == 1);
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if (init != State::S0) {
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@ -1207,7 +1211,7 @@ struct Abc9OpsPass : public Pass {
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log(" -prep_dff_unmap\n");
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log(" fill in previously created '$abc9_unmap' design to contain techmap rules\n");
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log(" for mapping *_$abc9_flop cells back into their original (* abc9_flop *)\n");
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log(" cells(including their original parameters).\n");
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log(" cells (including their original parameters).\n");
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log("\n");
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log(" -prep_delays\n");
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log(" insert `$__ABC9_DELAY' blackbox cells into the design to account for\n");
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