mirror of https://github.com/YosysHQ/yosys.git
Revert "Fix TODOs"
This reverts commit 8674a6c68d563908014d16671567459499c6dc99.
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6d68972619
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@ -103,6 +103,11 @@ code sigA sigB sigC sigD sigM clock
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}
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else
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sigM = P;
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// TODO: Check if necessary
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// This sigM could have no users if downstream $add
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// is narrower than $mul result, for example
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if (sigM.empty())
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reject;
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clock = port(dsp, \CLK, SigBit());
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endcode
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@ -154,6 +159,16 @@ match preAdd
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optional
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endmatch
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code sigA sigD
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// TODO: Check if this is necessary?
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if (preAdd) {
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sigA = port(preAdd, \A);
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sigD = port(preAdd, \B);
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if (GetSize(sigA) < GetSize(sigD))
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std::swap(sigA, sigD);
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}
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endcode
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// (4) If pre-adder was present, find match 'A' input for A2REG
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// If pre-adder was not present, move ADREG to A2REG
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// Then match 'A' input for A1REG
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@ -79,6 +79,11 @@ endcode
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// (attached to at most two $mux cells that implement clock-enable or
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// reset functionality, using the in_dffe subpattern)
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code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
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// TODO: Any downside to allowing this?
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// If this DSP implements an accumulator, do not attempt to match
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if (sigC == sigP)
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reject;
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argQ = sigC;
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subpattern(in_dffe);
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if (dff) {
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