mirror of https://github.com/YosysHQ/yosys.git
opt_expr: restore consume_x; use for coarse grained too
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495acf9815
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17f4e06247
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@ -543,13 +543,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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}
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}
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if (detect_const_and && (found_zero || found_inv || (!keepdc && found_undef))) {
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if (detect_const_and && (found_zero || found_inv || (!keepdc && found_undef && consume_x))) {
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cover("opt.opt_expr.const_and");
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replace_cell(assign_map, module, cell, "const_and", ID::Y, RTLIL::State::S0);
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goto next_cell;
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}
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if (detect_const_or && (found_one || found_inv || (!keepdc && found_undef))) {
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if (detect_const_or && (found_one || found_inv || (!keepdc && found_undef && consume_x))) {
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cover("opt.opt_expr.const_or");
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replace_cell(assign_map, module, cell, "const_or", ID::Y, RTLIL::State::S1);
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goto next_cell;
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@ -927,7 +927,7 @@ skip_fine_alu:
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if (input.match("**")) ACTION_DO_Y(x);
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if (input.match("1*")) ACTION_DO_Y(x);
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if (input.match("*1")) ACTION_DO_Y(x);
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if (!keepdc) {
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if (consume_x) {
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if (input.match(" *")) ACTION_DO_Y(0);
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if (input.match("* ")) ACTION_DO_Y(0);
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}
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@ -946,7 +946,7 @@ skip_fine_alu:
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if (input.match("**")) ACTION_DO_Y(x);
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if (input.match("0*")) ACTION_DO_Y(x);
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if (input.match("*0")) ACTION_DO_Y(x);
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if (!keepdc) {
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if (consume_x) {
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if (input.match(" *")) ACTION_DO_Y(1);
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if (input.match("* ")) ACTION_DO_Y(1);
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}
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@ -963,7 +963,7 @@ skip_fine_alu:
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if (input.match("01")) ACTION_DO_Y(1);
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if (input.match("10")) ACTION_DO_Y(1);
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if (input.match("11")) ACTION_DO_Y(0);
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if (!keepdc) {
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if (consume_x) {
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if (input.match(" *")) ACTION_DO_Y(0);
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if (input.match("* ")) ACTION_DO_Y(0);
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}
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@ -1149,7 +1149,7 @@ skip_fine_alu:
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goto next_cell;
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}
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if (!keepdc)
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if (!keepdc && consume_x)
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{
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bool identity_wrt_a = false;
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bool identity_wrt_b = false;
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