mirror of https://github.com/YosysHQ/yosys.git
Further clean up `passes/sat/freduce.cc`.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
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@ -828,9 +828,8 @@ struct FreducePass : public Pass {
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extra_args(args, argidx, design);
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int bitcount = 0;
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for (auto module : design->modules()) {
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if (design->selected(module))
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bitcount += FreduceWorker(design, module).run();
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for (auto module : design->selected_modules()) {
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bitcount += FreduceWorker(design, module).run();
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}
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log("Rewired a total of %d signal bits.\n", bitcount);
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