mirror of https://github.com/YosysHQ/yosys.git
Clean up pseudo-private member usage in `passes/sat/expose.cc`.
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1bf2bdf05b
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1197a43380
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@ -53,7 +53,7 @@ bool consider_cell(RTLIL::Design *design, std::set<RTLIL::IdString> &dff_cells,
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{
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if (cell->name[0] == '$' || dff_cells.count(cell->name))
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return false;
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if (cell->type[0] == '\\' && !design->modules_.count(cell->type))
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if (cell->type[0] == '\\' && (design->module(cell->type) == nullptr))
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return false;
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return true;
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}
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@ -314,26 +314,26 @@ struct ExposePass : public Pass {
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RTLIL::Module *first_module = NULL;
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std::set<RTLIL::IdString> shared_dff_wires;
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for (auto &mod_it : design->modules_)
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for (auto mod : design->modules())
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{
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if (!design->selected(mod_it.second))
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if (!design->selected(mod))
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continue;
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create_dff_dq_map(dff_dq_maps[mod_it.second], design, mod_it.second);
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create_dff_dq_map(dff_dq_maps[mod], design, mod);
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if (!flag_shared)
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continue;
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if (first_module == NULL) {
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for (auto &it : dff_dq_maps[mod_it.second])
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for (auto &it : dff_dq_maps[mod])
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shared_dff_wires.insert(it.first);
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first_module = mod_it.second;
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first_module = mod;
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} else {
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std::set<RTLIL::IdString> new_shared_dff_wires;
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for (auto &it : shared_dff_wires) {
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if (!dff_dq_maps[mod_it.second].count(it))
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if (!dff_dq_maps[mod].count(it))
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continue;
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if (!compare_wires(first_module->wires_.at(it), mod_it.second->wires_.at(it)))
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if (!compare_wires(first_module->wires_.at(it), mod->wires_.at(it)))
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continue;
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new_shared_dff_wires.insert(it);
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}
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@ -364,10 +364,8 @@ struct ExposePass : public Pass {
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{
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RTLIL::Module *first_module = NULL;
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for (auto &mod_it : design->modules_)
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for (auto module : design->modules())
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{
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RTLIL::Module *module = mod_it.second;
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if (!design->selected(module))
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continue;
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