mirror of https://github.com/YosysHQ/yosys.git
xilinx_dsp: add parameter defaults
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@ -120,7 +120,7 @@ endcode
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// reset functionality, using a subpattern discussed above)
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// If matched, treat 'A' input as input of ADREG
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code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock
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if (param(dsp, \ADREG).as_int() == 0) {
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if (param(dsp, \ADREG, 1).as_int() == 0) {
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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@ -176,7 +176,7 @@ code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock ffA2 ffA2cem
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// Only search for ffA2 if there was a pre-adder
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// (otherwise ffA2 would have been matched as ffAD)
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if (preAdd) {
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if (param(dsp, \AREG).as_int() == 0) {
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if (param(dsp, \AREG, 1).as_int() == 0) {
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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@ -237,7 +237,7 @@ endcode
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// (5) Match 'B' input for B2REG
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// If B2REG, then match 'B' input for B1REG
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code argQ ffB2 ffB2cemux ffB2rstmux ffB2cepol ffBrstpol sigB clock ffB1 ffB1cemux ffB1rstmux ffB1cepol
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if (param(dsp, \BREG).as_int() == 0) {
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if (param(dsp, \BREG, 1).as_int() == 0) {
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argQ = sigB;
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subpattern(in_dffe);
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if (dff) {
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@ -287,7 +287,7 @@ endcode
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// (6) Match 'D' input for DREG
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code argQ ffD ffDcemux ffDrstmux ffDcepol ffDrstpol sigD clock
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if (param(dsp, \DREG).as_int() == 0) {
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if (param(dsp, \DREG, 1).as_int() == 0) {
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argQ = sigD;
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subpattern(in_dffe);
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if (dff) {
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@ -308,7 +308,7 @@ endcode
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// (7) Match 'P' output that exclusively drives an MREG
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code argD ffM ffMcemux ffMrstmux ffMcepol ffMrstpol sigM sigP clock
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if (param(dsp, \MREG).as_int() == 0 && nusers(sigM) == 2) {
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if (param(dsp, \MREG, 1).as_int() == 0 && nusers(sigM) == 2) {
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argD = sigM;
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subpattern(out_dffe);
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if (dff) {
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@ -335,7 +335,7 @@ endcode
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// recognised in xilinx_dsp.cc).
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match postAdd
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// Ensure that Z mux is not already used
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if port(dsp, \OPMODE, SigSpec()).extract(4,3).is_fully_zero()
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if port(dsp, \OPMODE, SigSpec(0, 7)).extract(4,3).is_fully_zero()
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select postAdd->type.in($add)
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select GetSize(port(postAdd, \Y)) <= 48
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@ -363,7 +363,7 @@ endcode
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// (9) Match 'P' output that exclusively drives a PREG
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code argD ffP ffPcemux ffPrstmux ffPcepol ffPrstpol sigP clock
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if (param(dsp, \PREG).as_int() == 0) {
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if (param(dsp, \PREG, 1).as_int() == 0) {
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int users = 2;
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// If ffMcemux and no postAdd new-value net must have three users: ffMcemux, ffM and ffPcemux
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if (ffMcemux && !postAdd) users++;
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