mirror of https://github.com/YosysHQ/yosys.git
kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.
Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs.
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ec4c9267b3
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@ -2242,7 +2242,7 @@ gen_stmt:
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ast_stack.back()->children.push_back(node);
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ast_stack.push_back(node);
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} opt_arg_list ';'{
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ast_stack.pop_back();
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ast_stack.pop_back();
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};
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gen_stmt_block:
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@ -2413,19 +2413,19 @@ basic_expr:
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append_attr($$, $2);
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} |
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basic_expr OP_SHL attr basic_expr {
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$$ = new AstNode(AST_SHIFT_LEFT, $1, $4);
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$$ = new AstNode(AST_SHIFT_LEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
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append_attr($$, $3);
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} |
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basic_expr OP_SHR attr basic_expr {
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$$ = new AstNode(AST_SHIFT_RIGHT, $1, $4);
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$$ = new AstNode(AST_SHIFT_RIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
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append_attr($$, $3);
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} |
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basic_expr OP_SSHL attr basic_expr {
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$$ = new AstNode(AST_SHIFT_SLEFT, $1, $4);
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$$ = new AstNode(AST_SHIFT_SLEFT, $1, new AstNode(AST_TO_UNSIGNED, $4));
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append_attr($$, $3);
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} |
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basic_expr OP_SSHR attr basic_expr {
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$$ = new AstNode(AST_SHIFT_SRIGHT, $1, $4);
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$$ = new AstNode(AST_SHIFT_SRIGHT, $1, new AstNode(AST_TO_UNSIGNED, $4));
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append_attr($$, $3);
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} |
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basic_expr '<' attr basic_expr {
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@ -783,6 +783,14 @@ namespace {
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return v;
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}
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int param_bool(RTLIL::IdString name, bool expected)
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{
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int v = param_bool(name);
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if (v != expected)
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error(__LINE__);
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return v;
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}
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void param_bits(RTLIL::IdString name, int width)
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{
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param(name);
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@ -869,13 +877,23 @@ namespace {
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return;
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}
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if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) {
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if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
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param_bool(ID(A_SIGNED));
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param_bool(ID(B_SIGNED), /*expected=*/false);
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port(ID::A, param(ID(A_WIDTH)));
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port(ID::B, param(ID(B_WIDTH)));
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port(ID::Y, param(ID(Y_WIDTH)));
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check_expected(/*check_matched_sign=*/false);
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return;
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}
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if (cell->type.in(ID($shift), ID($shiftx))) {
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param_bool(ID(A_SIGNED));
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param_bool(ID(B_SIGNED));
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port(ID::A, param(ID(A_WIDTH)));
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port(ID::B, param(ID(B_WIDTH)));
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port(ID::Y, param(ID(Y_WIDTH)));
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check_expected(false);
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check_expected(/*check_matched_sign=*/false);
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return;
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}
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@ -957,7 +975,7 @@ namespace {
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port(ID::A, param(ID(A_WIDTH)));
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port(ID::B, param(ID(B_WIDTH)));
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port(ID::Y, param(ID(Y_WIDTH)));
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check_expected(false);
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check_expected(/*check_matched_sign=*/false);
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return;
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}
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