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abc9_ops: add -prep_bypass for auto bypass boxes; refactor 

Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
This commit is contained in:
Eddie Hung 2020-04-21 12:22:39 -07:00
parent bb840cca9c
commit 7cd3f4a79b
11 changed files with 714 additions and 988 deletions
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64
passes/techmap/abc9.cc
View File

@ -275,22 +275,31 @@ struct Abc9Pass : public ScriptPass
void script() YS_OVERRIDE
{
if (check_label("check")) {
run("abc9_ops -check");
if (help_mode)
run("abc9_ops -check [-dff]", "(option if -dff)");
else
run(stringf("abc9_ops -check %s", dff_mode ? "-dff" : ""));
}
if (check_label("dff", "(only if -dff)")) {
if (dff_mode || help_mode) {
run("abc9_ops -prep_dff_hier"); // derive all used (* abc9_flop *) modules,
// create stubs in $abc9_unmap design
run("design -stash $abc9");
run("design -copy-from $abc9 @$abc9_flops"); // copy derived modules in
run("proc");
run("wbflip");
run("techmap");
run("opt");
if (check_label("map")) {
if (help_mode)
run("abc9_ops -prep_hier -prep_bypass [-prep_dff -dff]", "(option if -dff)");
else
run(stringf("abc9_ops -prep_hier -prep_bypass %s", dff_mode ? "-prep_dff -dff" : ""));
if (dff_mode) {
run("design -copy-to $abc9_map @$abc9_flops", "(only if -dff)");
run("select -unset $abc9_flops", " (only if -dff)");
}
run("design -stash $abc9");
run("design -load $abc9_map");
run("proc");
run("wbflip");
run("techmap");
run("opt");
if (dff_mode) {
if (!help_mode)
active_design->scratchpad_unset("abc9_ops.prep_dff_map.did_something");
run("abc9_ops -prep_dff_map"); // rewrite specify
run("abc9_ops -prep_dff_map", "(only if -dff)"); // rewrite specify
bool did_something = help_mode || active_design->scratchpad_get_bool("abc9_ops.prep_dff_map.did_something");
if (did_something) {
// select all $_DFF_[NP]_
@ -299,6 +308,8 @@ struct Abc9Pass : public ScriptPass
// lastly remove $_DFF_[NP]_ cells
run("setattr -set submod \"$abc9_flop\" t:$_DFF_?_ %ci* %co* t:$_DFF_?_ %d");
run("submod");
run("setattr -mod -set whitebox 1 -set abc9_flop 1 -set abc9_box 1 *_$abc9_flop");
run("abc9_ops -prep_dff_unmap");
run("design -copy-to $abc9 *_$abc9_flop"); // copy submod out
run("delete *_$abc9_flop");
if (help_mode) {
@ -313,21 +324,13 @@ struct Abc9Pass : public ScriptPass
run(stringf("rename %s_$abc9_flop _TECHMAP_REPLACE_", module->name.c_str()));
}
}
run("design -stash $abc9_map");
}
run("design -load $abc9");
run("design -delete $abc9");
run("select -unset $abc9_flops");
if (did_something) { // techmap user design into submod + $_DFF_[NP]_
run("techmap -wb -max_iter 1 -map %$abc9_map -map +/abc9_map.v");
run("design -delete $abc9_map");
run("setattr -mod -set whitebox 1 -set abc9_flop 1 -set abc9_box 1 *_$abc9_flop");
run("abc9_ops -prep_dff_unmap"); // implement $abc9_unmap design
}
else
run("techmap -wb -max_iter 1 -map +/abc9_map.v");
}
run("design -stash $abc9_map");
run("design -load $abc9");
run("design -delete $abc9");
run("techmap -wb -max_iter 1 -map %$abc9_map -map +/abc9_map.v");
run("design -delete $abc9_map");
}
if (check_label("pre")) {
@ -353,9 +356,10 @@ struct Abc9Pass : public ScriptPass
run("aigmap");
run("design -stash $abc9_holes");
run("design -load $abc9");
run("design -delete $abc9");
}
if (check_label("map")) {
if (check_label("exe")) {
run("aigmap");
if (help_mode) {
run("foreach module in selection");
@ -430,12 +434,10 @@ struct Abc9Pass : public ScriptPass
}
}
if (check_label("post")) {
if (dff_mode || help_mode) {
run("techmap -wb -map %$abc9_unmap", "(only if -dff)"); // techmap user design from submod back to original cell
if (check_label("unmap")) {
run("techmap -wb -map %$abc9_unmap -map +/abc9_unmap.v"); // techmap user design from submod back to original cell
// ($_DFF_[NP]_ already shorted by -reintegrate)
run("design -delete $abc9_unmap", " (only if -dff)");
}
run("design -delete $abc9_unmap");
if (saved_designs.count("$abc9_holes") || help_mode)
run("design -delete $abc9_holes");
}

712
passes/techmap/abc9_ops.cc
View File

@ -34,13 +34,10 @@ inline std::string remap_name(RTLIL::IdString abc9_name)
return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
}
void check(RTLIL::Design *design)
void check(RTLIL::Design *design, bool dff_mode)
{
dict<IdString,IdString> box_lookup;
for (auto m : design->modules()) {
if (m->name.begins_with("$paramod"))
continue;
auto flop = m->get_bool_attribute(ID::abc9_flop);
auto it = m->attributes.find(ID::abc9_box_id);
if (!flop) {
@ -88,6 +85,469 @@ void check(RTLIL::Design *design)
log_error("Module '%s' with (* abc9_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs);
}
}
if (dff_mode) {
pool<IdString> unsupported{
ID($adff), ID($dlatch), ID($dlatchsr), ID($sr),
ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_),
ID($_DLATCH_N_), ID($_DLATCH_P_),
ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_),
ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_),
ID($_SR_NN_), ID($_SR_NP_), ID($_SR_PN_), ID($_SR_PP_)
};
pool<IdString> processed;
for (auto module : design->selected_modules())
for (auto cell : module->cells()) {
auto inst_module = design->module(cell->type);
if (!inst_module)
continue;
if (!inst_module->attributes.count(ID::abc9_flop))
continue;
auto derived_type = inst_module->derive(design, cell->parameters);
if (!processed.insert(derived_type).second)
continue;
if (inst_module->get_blackbox_attribute(true /* ignore_wb */))
log_error("Module '%s' with (* abc9_flop *) is a blackbox.\n", log_id(derived_type));
auto derived_module = design->module(derived_type);
if (derived_module->has_processes())
Pass::call_on_module(design, derived_module, "proc");
if (derived_module->get_bool_attribute(ID::abc9_flop)) {
bool found = false;
for (auto derived_cell : derived_module->cells())
if (derived_cell->type.in(ID($dff), ID($_DFF_N_), ID($_DFF_P_))) {
if (found)
log_error("Module '%s' with (* abc9_flop *) contains more than one $_DFF_[NP]_ cell.\n", log_id(derived_module));
found = true;
SigBit Q = derived_cell->getPort(ID::Q);
log_assert(GetSize(Q.wire) == 1);
if (!Q.wire->port_output)
log_error("Module '%s' contains a %s cell where its 'Q' port does not drive a module output!\n", log_id(derived_module), log_id(derived_cell->type));
Const init = Q.wire->attributes.at(ID::init, State::Sx);
log_assert(GetSize(init) == 1);
}
else if (unsupported.count(derived_cell->type)) {
log_error("Module '%s' with (* abc9_flop *) contains a %s cell, which is not supported for sequential synthesis.\n", log_id(derived_module), log_id(derived_cell->type));
}
}
}
}
}
void prep_hier(RTLIL::Design *design, bool dff_mode)
{
auto r = saved_designs.emplace("$abc9_unmap", nullptr);
if (r.second)
r.first->second = new Design;
Design *unmap_design = r.first->second;
pool<IdString> seq_types{
ID($dff), ID($dffsr), ID($adff),
ID($dlatch), ID($dlatchsr), ID($sr),
ID($mem),
ID($_DFF_N_), ID($_DFF_P_),
ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_),
ID($_DFF_N_), ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
ID($_DFF_P_), ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_),
ID($_DLATCH_N_), ID($_DLATCH_P_),
ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_),
ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_),
ID($_SR_NN_), ID($_SR_NP_), ID($_SR_PN_), ID($_SR_PP_)
};
for (auto module : design->selected_modules())
for (auto cell : module->cells()) {
auto inst_module = design->module(cell->type);
if (!inst_module)
continue;
auto derived_type = inst_module->derive(design, cell->parameters);
auto derived_module = design->module(derived_type);
if (derived_module->get_blackbox_attribute(true /* ignore_wb */))
continue;
if (inst_module->attributes.count(ID::abc9_flop) && !dff_mode)
continue;
if (!inst_module->attributes.count(ID::abc9_box) && !inst_module->attributes.count(ID::abc9_flop))
continue;
if (!unmap_design->module(derived_type)) {
if (derived_module->has_processes())
Pass::call_on_module(design, derived_module, "proc");
if (derived_module->get_bool_attribute(ID::abc9_flop)) {
for (auto derived_cell : derived_module->cells())
if (derived_cell->type.in(ID($dff), ID($_DFF_N_), ID($_DFF_P_))) {
SigBit Q = derived_cell->getPort(ID::Q);
Const init = Q.wire->attributes.at(ID::init, State::Sx);
log_assert(GetSize(init) == 1);
// Block sequential synthesis on cells with (* init *) != 1'b0
// because ABC9 doesn't support them
if (init != State::S0) {
log_warning("Module '%s' contains a %s cell with non-zero initial state -- this is not unsupported for ABC9 sequential synthesis. Treating as a blackbox.\n", log_id(derived_module), log_id(derived_cell->type));
// TODO: still necessary?
// Do not use set_bool_attribute() as it will unset the value
// and (attributes.count(ID::abc9_flop) will fail)
derived_module->attributes[ID::abc9_flop] = false;
goto skip_cell;
}
break;
}
}
else if (derived_module->get_bool_attribute(ID::abc9_box)) {
bool found = false;
for (auto derived_cell : derived_module->cells())
if (seq_types.count(derived_cell->type)) {
found = true;
break;
}
if (!found) {
derived_module->set_bool_attribute(ID::abc9_box, false);
log_assert(!derived_module->attributes.count(ID::abc9_box));
goto skip_cell;
}
// TODO: still necessary?
// Do not use set_bool_attribute() as it will unset the value
// and (attributes.count(ID::abc9_box) will fail)
derived_module->attributes[ID::abc9_box] = false;
}
if (derived_type != cell->type) {
auto unmap_module = unmap_design->addModule(derived_type);
for (auto port : derived_module->ports) {
auto w = unmap_module->addWire(port, derived_module->wire(port));
// Do not propagate (* init *) values inside the box
if (w->port_output)
w->attributes.erase(ID::init);
}
unmap_module->ports = derived_module->ports;
unmap_module->check();
auto replace_cell = unmap_module->addCell(ID::_TECHMAP_REPLACE_, cell->type);
for (const auto &conn : cell->connections()) {
auto w = unmap_module->wire(conn.first);
log_assert(w);
replace_cell->setPort(conn.first, w);
}
replace_cell->parameters = cell->parameters;
}
}
cell->type = derived_type;
cell->parameters.clear();
skip_cell: ;
}
}
void prep_bypass(RTLIL::Design *design)
{
auto r = saved_designs.emplace("$abc9_map", nullptr);
if (r.second)
r.first->second = new Design;
Design *map_design = r.first->second;
r = saved_designs.emplace("$abc9_unmap", nullptr);
if (r.second)
r.first->second = new Design;
Design *unmap_design = r.first->second;
pool<IdString> processed;
for (auto module : design->selected_modules())
for (auto cell : module->cells()) {
if (!processed.insert(cell->type).second)
continue;
auto inst_module = design->module(cell->type);
if (!inst_module)
continue;
auto derived_type = inst_module->derive(design, cell->parameters);
inst_module = design->module(derived_type);
log_assert(inst_module);
if (inst_module->get_blackbox_attribute(true /* ignore_wb */))
continue;
// Skip if (* abc9_box *) exists or is true
auto it = inst_module->attributes.find(ID::abc9_box);
if (it == inst_module->attributes.end() || it->second.as_bool())
continue;
// The idea is to create two techmap designs, one which maps:
//
// box u0 (.i(i), .o(o));
//
// to
//
// wire $abc9$o;
// box u0 (.i(i), .o($abc9_byp$o));
// box_$abc9_byp (.i(i), .$abc9_byp$o($abc9_byp$o), .o(o));
//
// the purpose being to move the (* abc9_box *) status from 'box'
// (which is stateful) to 'box_$abc9_byp' (which becomes a new
// combinatorial black- (not white-) box with all state elements
// removed). This has the effect of preserving any combinatorial
// paths through an otherwise sequential primitive -- e.g. LUTRAMs.
//
// The unmap design performs the reverse:
//
// wire $abc9$o;
// box u0 (.i(i), .o($abc9_byp$o));
// box_$abc9_byp (.i(i), .$abc9_byp$o($abc9_byp$o), .o(o));
//
// to:
//
// wire $abc9$o;
// box u0 (.i(i), .o($abc9_byp$o));
// assign o = $abc9_byp$o;
// Copy derived_module into map_design, with the same interface
// and duplicate $abc9$* wires for its output ports
auto map_module = map_design->addModule(cell->type);
for (auto port_name : inst_module->ports) {
auto w = map_module->addWire(port_name, inst_module->wire(port_name));
if (w->port_output)
w->attributes.erase(ID::init);
}
map_module->ports = inst_module->ports;
map_module->check();
map_module->set_bool_attribute(ID::whitebox);
// Create the bypass module in the user design, which has the same
// interface as the derived module but with additional input
// ports driven by the outputs of the replaced cell
auto bypass_module = design->addModule(cell->type.str() + "_$abc9_byp");
for (auto port_name : inst_module->ports) {
auto port = inst_module->wire(port_name);
if (!port->port_output)
continue;
auto dst = bypass_module->addWire(port_name, port);
auto src = bypass_module->addWire("$abc9byp$" + port_name.str(), GetSize(port));
src->port_input = true;
// For these new input ports driven by the replaced
// cell, then create a new simple-path specify entry:
// (input => output) = 0
auto specify = bypass_module->addCell(NEW_ID, ID($specify2));
specify->setPort(ID::EN, State::S1);
specify->setPort(ID::SRC, src);
specify->setPort(ID::DST, dst);
specify->setParam(ID::FULL, 0);
specify->setParam(ID::SRC_WIDTH, GetSize(src));
specify->setParam(ID::DST_WIDTH, GetSize(dst));
specify->setParam(ID::SRC_DST_PEN, 0);
specify->setParam(ID::SRC_DST_POL, 0);
specify->setParam(ID::T_RISE_MIN, 0);
specify->setParam(ID::T_RISE_TYP, 0);
specify->setParam(ID::T_RISE_MAX, 0);
specify->setParam(ID::T_FALL_MIN, 0);
specify->setParam(ID::T_FALL_TYP, 0);
specify->setParam(ID::T_FALL_MAX, 0);
}
bypass_module->set_bool_attribute(ID::blackbox);
bypass_module->set_bool_attribute(ID::abc9_box);
// Copy any 'simple' (combinatorial) specify paths from
// the derived module into the bypass module, if EN
// is not false and SRC/DST are driven only by
// module ports; create new input port if one doesn't
// already exist
for (auto cell : inst_module->cells()) {
if (cell->type != ID($specify2))
continue;
auto EN = cell->getPort(ID::EN).as_bit();
SigBit newEN;
if (!EN.wire && EN != State::S1)
continue;
auto SRC = cell->getPort(ID::SRC);
for (const auto &c : SRC.chunks())
if (c.wire && !c.wire->port_input) {
SRC = SigSpec();
break;
}
if (SRC.empty())
continue;
auto DST = cell->getPort(ID::DST);
for (const auto &c : DST.chunks())
if (c.wire && !c.wire->port_output) {
DST = SigSpec();
break;
}
if (DST.empty())
continue;
auto rw = [bypass_module](RTLIL::SigSpec &sig)
{
SigSpec new_sig;
for (auto c : sig.chunks()) {
if (c.wire) {
auto port = bypass_module->wire(c.wire->name);
if (!port)
port = bypass_module->addWire(c.wire->name, c.wire);
c.wire = port;
}
new_sig.append(std::move(c));
}
sig = std::move(new_sig);
};
auto specify = bypass_module->addCell(NEW_ID, cell);
specify->rewrite_sigspecs(rw);
}
bypass_module->fixup_ports();
// Create an _TECHMAP_REPLACE_ cell identical to the original cell,
// and a bypass cell that has the same inputs/outputs as the
// original cell, but with additional inputs taken from the
// replaced cell
auto replace_cell = map_module->addCell(ID::_TECHMAP_REPLACE_, cell->type);
auto bypass_cell = map_module->addCell(NEW_ID, cell->type.str() + "_$abc9_byp");
for (const auto &conn : cell->connections()) {
auto port = map_module->wire(conn.first);
if (cell->input(conn.first)) {
replace_cell->setPort(conn.first, port);
if (bypass_module->wire(conn.first))
bypass_cell->setPort(conn.first, port);
}
if (cell->output(conn.first)) {
bypass_cell->setPort(conn.first, port);
auto n = "$abc9byp$" + conn.first.str();
auto w = map_module->addWire(n, GetSize(conn.second));
replace_cell->setPort(conn.first, w);
bypass_cell->setPort(n, w);
}
}
// Lastly, create a new module in the unmap_design that shorts
// out the bypass cell back to leave the replace cell behind
// driving the outputs
auto unmap_module = unmap_design->addModule(cell->type.str() + "_$abc9_byp");
for (auto port_name : inst_module->ports) {
auto w = unmap_module->addWire(port_name, inst_module->wire(port_name));
if (w->port_output) {
w->attributes.erase(ID::init);
auto w2 = unmap_module->addWire("$abc9byp$" + port_name.str(), GetSize(w));
w2->port_input = true;
unmap_module->connect(w, w2);
}
}
unmap_module->fixup_ports();
}
}
void prep_dff(RTLIL::Design *design)
{
auto r = design->selection_vars.insert(std::make_pair(ID($abc9_flops), RTLIL::Selection(false)));
auto &modules_sel = r.first->second;
for (auto module : design->selected_modules())
for (auto cell : module->cells()) {
if (modules_sel.selected_whole_module(cell->type))
continue;
auto inst_module = design->module(cell->type);
if (!inst_module)
continue;
if (!inst_module->attributes.count(ID::abc9_flop))
continue;
auto derived_type = inst_module->derive(design, cell->parameters);
auto derived_module = design->module(derived_type);
log_assert(derived_module);
if (!derived_module->get_bool_attribute(ID::abc9_flop))
continue;
log_assert(!derived_module->get_blackbox_attribute(true /* ignore_wb */));
modules_sel.select(derived_module);
}
}
void prep_dff_map(RTLIL::Design *design)
{
for (auto module : design->modules()) {
vector<Cell*> specify_cells;
SigBit Q;
Cell* dff_cell = nullptr;
if (!module->get_bool_attribute(ID::abc9_flop))
continue;
for (auto cell : module->cells())
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
log_assert(!dff_cell);
dff_cell = cell;
Q = cell->getPort(ID::Q);
log_assert(GetSize(Q.wire) == 1);
}
else if (cell->type.in(ID($specify3), ID($specrule)))
specify_cells.emplace_back(cell);
log_assert(dff_cell);
// Add dummy buffers for all module inputs/outputs
// to ensure that these ports exists in the flop box
// created by later submod pass
for (auto port_name : module->ports) {
auto port = module->wire(port_name);
log_assert(GetSize(port) == 1);
auto c = module->addBufGate(NEW_ID, port, module->addWire(NEW_ID));
// Need to set (* keep *) otherwise opt_clean
// inside submod will blow it away
c->set_bool_attribute(ID::keep);
}
// Add an additional buffer that drives $_DFF_[NP]_.D
// so that the flop box will have an output
SigBit D = module->addWire(NEW_ID);
Cell *c = module->addBufGate(NEW_ID, dff_cell->getPort(ID::D), D);
c->set_bool_attribute(ID::keep);
dff_cell->setPort(ID::D, D);
// Rewrite $specify cells that end with $_DFF_[NP]_.Q
// to $_DFF_[NP]_.D since it will be moved into
// the submodule
for (auto cell : specify_cells) {
auto DST = cell->getPort(ID::DST);
DST.replace(Q, D);
cell->setPort(ID::DST, DST);
}
design->scratchpad_set_bool("abc9_ops.prep_dff_map.did_something", true);
}
}
void prep_dff_unmap(RTLIL::Design *design)
{
Design *unmap_design = saved_designs.at("$abc9_unmap");
for (auto module : design->modules()) {
if (!module->get_bool_attribute(ID::abc9_flop) || module->get_bool_attribute(ID::abc9_box))
continue;
auto unmap_module = unmap_design->addModule(module->name.str() + "_$abc9_flop");
auto replace_cell = unmap_module->addCell(ID::_TECHMAP_REPLACE_, module->name);
for (auto port_name : module->ports) {
auto w = unmap_module->addWire(port_name, module->wire(port_name));
// Do not propagate (* init *) values inside the box
if (w->port_output)
w->attributes.erase(ID::init);
replace_cell->setPort(port_name, w);
}
// Add new ports appearing in "_$abc9_flop"
auto box_module = design->module(unmap_module->name);
log_assert(box_module);
for (auto port_name : box_module->ports) {
auto port = box_module->wire(port_name);
auto unmap_port = unmap_module->wire(port_name);
if (!unmap_port)
unmap_port = unmap_module->addWire(port_name, port);
else
unmap_port->port_id = port->port_id;
}
unmap_module->ports = box_module->ports;
unmap_module->check();
}
}
void mark_scc(RTLIL::Module *module)
@ -119,168 +579,6 @@ void mark_scc(RTLIL::Module *module)
}
}
void prep_dff_hier(RTLIL::Design *design)
{
auto r YS_ATTRIBUTE(unused) = design->selection_vars.insert(std::make_pair(ID($abc9_flops), RTLIL::Selection(false)));
log_assert(r.second);
auto &modules_sel = design->selection_vars.at(ID($abc9_flops));
Design *unmap_design = new Design;
for (auto module : design->selected_modules())
for (auto cell : module->cells()) {
auto inst_module = design->module(cell->type);
if (inst_module && inst_module->attributes.count(ID::abc9_flop)) {
if (inst_module->get_blackbox_attribute(true /* ignore_wb */))
log_error("Module '%s' with (* abc9_flop *) is not a whitebox.\n", log_id(inst_module));
// Derive modules for all instantiations of (* abc9_flop *)
auto derived_type = inst_module->derive(design, cell->parameters);
auto derived_module = design->module(derived_type);
if (!derived_module->get_bool_attribute(ID::abc9_flop))
continue;
// And create the stub in the $abc9_unmap design
if (!modules_sel.selected_whole_module(derived_type)) {
if (derived_type != cell->type)
modules_sel.select(inst_module);
modules_sel.select(derived_module);
auto unmap_module = unmap_design->addModule(derived_type.str() + "_$abc9_flop");
auto unmap_cell = unmap_module->addCell(ID::_TECHMAP_REPLACE_, cell->type);
for (const auto &conn : cell->connections())
unmap_cell->setPort(conn.first, SigSpec());
unmap_cell->parameters = cell->parameters;
}
}
}
auto r2 YS_ATTRIBUTE(unused) = saved_designs.emplace("$abc9_unmap", unmap_design);
log_assert(r2.second);
}
void prep_dff_map(RTLIL::Design *design)
{
Design *unmap_design = saved_designs.at("$abc9_unmap");
for (auto module : design->modules()) {
vector<Cell*> specify_cells;
SigBit D, Q;
Cell *c;
Cell* dff_cell = nullptr;
// If module has a public name (i.e. not $paramod) and it doesn't exist
// in the $abc9_unmap then it means only derived modules were
// instantiated, so make this a blackbox
if (module->name[0] == '\\' && !unmap_design->module(module->name.str() + "_$abc9_flop")) {
module->makeblackbox();
module->set_bool_attribute(ID::blackbox, false);
module->set_bool_attribute(ID::whitebox, true);
continue;
}
for (auto cell : module->cells())
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
if (dff_cell)
log_error("Module '%s' with (* abc9_flop *) contains more than one $_DFF_[NP]_ cell.\n", log_id(module));
dff_cell = cell;
// Block sequential synthesis on cells with (* init *) != 1'b0
// because ABC9 doesn't support them
Q = cell->getPort(ID::Q);
log_assert(GetSize(Q.wire) == 1);
if (!Q.wire->port_output)
log_error("Module '%s' contains a %s cell where its 'Q' port does not drive a module output!\n", log_id(module), log_id(cell->type));
Const init = Q.wire->attributes.at(ID::init, State::Sx);
log_assert(GetSize(init) == 1);
if (init != State::S0) {
log_warning("Module '%s' contains a %s cell with non-zero initial state -- this is not unsupported for ABC9 sequential synthesis. Treating as a blackbox.\n", log_id(module), log_id(cell->type));
module->makeblackbox();
module->set_bool_attribute(ID::blackbox, false);
auto wire = module->addWire(ID(_TECHMAP_FAIL_));
wire->set_bool_attribute(ID::keep);
module->connect(wire, State::S1);
goto continue_outer_loop;
}
}
else if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_),
ID($__DFFE_NN0), ID($__DFFE_NN1), ID($__DFFE_NP0), ID($__DFFE_NP1),
ID($__DFFE_PN0), ID($__DFFE_PN1), ID($__DFFE_PP0), ID($__DFFE_PP1)))
log_error("Module '%s' with (* abc9_flop *) contains an asynchronous $_DFFE?_[NP][NP][01]_? cell, which is not supported for sequential synthesis.\n", log_id(module));
else if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
specify_cells.emplace_back(cell);
if (!dff_cell)
log_error("Module '%s' with (* abc9_flop *) does not any contain $_DFF_[NP]_ cells.\n", log_id(module));
// Add dummy buffers for all module inputs/outputs
// to ensure that these ports exists in the flop box
// created by later submod pass
for (auto port_name : module->ports) {
auto port = module->wire(port_name);
log_assert(GetSize(port) == 1);
auto c = module->addBufGate(NEW_ID, port, module->addWire(NEW_ID));
// Need to set (* keep *) otherwise opt_clean
// inside submod will blow it away
c->set_bool_attribute(ID::keep);
}
// Add an additional buffer that drives $_DFF_[NP]_.D
// so that the flop box will have an output
D = module->addWire(NEW_ID);
c = module->addBufGate(NEW_ID, dff_cell->getPort(ID::D), D);
c->set_bool_attribute(ID::keep);
dff_cell->setPort(ID::D, D);
// Rewrite $specify cells that end with $_DFF_[NP]_.Q
// to $_DFF_[NP]_.D since it will be moved into
// the submodule
for (auto cell : specify_cells) {
auto DST = cell->getPort(ID::DST);
DST.replace(Q, D);
cell->setPort(ID::DST, DST);
}
design->scratchpad_set_bool("abc9_ops.prep_dff_map.did_something", true);
continue_outer_loop: ;
}
}
void prep_dff_unmap(RTLIL::Design *design)
{
Design *unmap_design = saved_designs.at("$abc9_unmap");
// Create the reverse techmap rule -- (* abc9_box *) back to flop
for (auto module : unmap_design->modules()) {
auto flop_module = design->module(module->name.str());
if (!flop_module)
continue; // May not exist if init = 1'b1
auto unmap_module = unmap_design->module(flop_module->name);
log_assert(unmap_module);
for (auto port : flop_module->ports) {
auto w = unmap_module->addWire(port, flop_module->wire(port));
// Do not propagate (* init *) values inside the box
w->attributes.erase(ID::init);
}
unmap_module->ports = flop_module->ports;
unmap_module->check();
auto unmap_cell = unmap_module->cell(ID::_TECHMAP_REPLACE_);
log_assert(unmap_cell);
for (const auto &conn : unmap_cell->connections()) {
auto rhs = unmap_module->wire(conn.first);
log_assert(rhs);
unmap_cell->setPort(conn.first, rhs);
}
}
}
void prep_xaiger(RTLIL::Module *module, bool dff)
{
auto design = module->design;
@ -477,7 +775,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
continue;
if (!inst_module->get_blackbox_attribute())
continue;
if (inst_module->attributes.count(ID::abc9_box))
if (inst_module->get_bool_attribute(ID::abc9_box))
continue;
IdString derived_type = inst_module->derive(design, cell->parameters);
inst_module = design->module(derived_type);
@ -630,7 +928,12 @@ void prep_box(RTLIL::Design *design)
dict<IdString,std::vector<IdString>> box_ports;
for (auto module : design->modules()) {
if (!module->attributes.erase(ID::abc9_box))
auto it = module->attributes.find(ID::abc9_box);
if (it == module->attributes.end())
continue;
bool box = it->second.as_bool();
module->attributes.erase(it);
if (!box)
continue;
auto r = module->attributes.insert(ID::abc9_box_id);
@ -758,8 +1061,6 @@ void prep_box(RTLIL::Design *design)
auto &t = timing.setup_module(module);
if (t.comb.empty())
log_error("Module '%s' with (* abc9_box *) has no timing (and thus no connectivity) information.\n", log_id(module));
if (!t.arrival.empty() || !t.required.empty())
log_error("Module '%s' with (* abc9_box *) has setup and/or edge-sensitive timing information.\n", log_id(module));
for (const auto &o : outputs) {
first = true;
@ -1226,21 +1527,38 @@ struct Abc9OpsPass : public Pass {
log(" check that the design is valid, e.g. (* abc9_box_id *) values are unique,\n");
log(" (* abc9_carry *) is only given for one input/output port, etc.\n");
log("\n");
log(" -prep_dff_hier\n");
log(" derive all cells with a type instantiating an (* abc9_flop *) module.\n");
log(" store such modules in named selection '$abc9_flops'. create stubs within\n");
log(" a new '$abc9_unmap' design to be used by -prep_dff_unmap.\n");
log(" -prep_hier\n");
log(" derive all used (* abc9_box *) requiring bypass, or (* abc9_flop *) (if\n");
log(" -dff option) whitebox modules. with (* abc9_box *) modules, bypassing is\n");
log(" necessary if sequential elements (e.g. $dff, $mem, etc.) are discovered\n");
log(" inside, to ensure that any combinatorial paths are correctly captured.\n");
log(" with (* abc9_flop *) modules, only those containing $dff/$_DFF_[NP]_\n");
log(" cells with zero initial state -- due to an ABC limitation -- will be\n");
log(" derived. for such derived modules, add a rule inside the '$abc9_unmap'\n");
log(" design that can map a cell instantiating a derived module back to the\n");
log(" original cell with parameters.\n");
log("\n");
log(" -prep_bypass\n");
log(" create techmap rules in the '$abc9_map' and '$abc9_unmap' designs for\n");
log(" bypassing sequential (* abc9_box *) modules using a combinatorial box\n");
log(" (named *_$abc9_byp) that has inherited all its $specify2 (simple path)\n");
log(" cells.\n");
log("\n");
log(" -prep_dff\n");
log(" select all (* abc9_flop *) modules instantiated in the design and store\n");
log(" in the named selection '$abc9_flops'.\n");
log("\n");
log(" -prep_dff_map\n");
log(" within (* abc9_flop *) modules, move all $specify{2,3}/$specrule cells\n");
log(" that share a 'DST' port with the $_DFF_[NP]_.Q port from this 'Q' port to\n");
log(" the DFF's 'D' port. this is to prepare such specify cells to be moved into\n");
log(" a submodule.\n");
log(" within (* abc9_flop *) modules, attach dummy buffers to all ports and move\n");
log(" all $specify3/$specrule cells that share a 'DST' port with the $_DFF_[NP]_.Q\n");
log(" port from this 'Q' port to the DFF's 'D' port. this is to ensure that all\n");
log(" module ports will exist in any submodule, and prepare such specify cells to\n");
log(" be moved within.\n");
log("\n");
log(" -prep_dff_unmap\n");
log(" fill in previously created '$abc9_unmap' design to contain techmap rules\n");
log(" for mapping *_$abc9_flop cells back into their original (* abc9_flop *)\n");
log(" cells (including their original parameters).\n");
log(" populate the '$abc9_unmap' design with techmap rules for mapping *_$abc9_flop\n");
log(" cells back into their derived cell types (where the rules created by\n");
log(" -prep_hier will then map back to the original cell with parameters).\n");
log("\n");
log(" -prep_delays\n");
log(" insert `$__ABC9_DELAY' blackbox cells into the design to account for\n");
@ -1288,7 +1606,9 @@ struct Abc9OpsPass : public Pass {
bool check_mode = false;
bool prep_delays_mode = false;
bool mark_scc_mode = false;
bool prep_dff_hier_mode = false, prep_dff_map_mode = false, prep_dff_unmap_mode = false;
bool prep_hier_mode = false;
bool prep_bypass_mode = false;
bool prep_dff_mode = false, prep_dff_map_mode = false, prep_dff_unmap_mode = false;
bool prep_xaiger_mode = false;
bool prep_lut_mode = false;
bool prep_box_mode = false;
@ -1312,8 +1632,18 @@ struct Abc9OpsPass : public Pass {
valid = true;
continue;
}
if (arg == "-prep_dff_hier") {
prep_dff_hier_mode = true;
if (arg == "-prep_hier") {
prep_hier_mode = true;
valid = true;
continue;
}
if (arg == "-prep_bypass") {
prep_bypass_mode = true;
valid = true;
continue;
}
if (arg == "-prep_dff") {
prep_dff_mode = true;
valid = true;
continue;
}
@ -1376,13 +1706,17 @@ struct Abc9OpsPass : public Pass {
if (!valid)
log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff[123],lut,box}, -write_{lut,box}, -reintegrate must be specified.\n");
if (dff_mode && !prep_delays_mode && !prep_xaiger_mode && !reintegrate_mode)
log_cmd_error("'-dff' option is only relevant for -prep_{delay,xaiger} or -reintegrate.\n");
if (dff_mode && !check_mode && !prep_hier_mode && !prep_delays_mode && !prep_xaiger_mode && !reintegrate_mode)
log_cmd_error("'-dff' option is only relevant for -prep_{hier,delay,xaiger} or -reintegrate.\n");
if (check_mode)
check(design);
if (prep_dff_hier_mode)
prep_dff_hier(design);
check(design, dff_mode);
if (prep_hier_mode)
prep_hier(design, dff_mode);
if (prep_bypass_mode)
prep_bypass(design);
if (prep_dff_mode)
prep_dff(design);
if (prep_dff_map_mode)
prep_dff_map(design);
if (prep_dff_unmap_mode)

2
techlibs/ecp5/synth_ecp5.cc
View File

@ -316,7 +316,7 @@ struct SynthEcp5Pass : public ScriptPass
if (!nodffe)
run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
if ((abc9 && dff) || help_mode)
run("zinit -all", "(-abc9 and -dff only)");
run("zinit -all t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "(only if -abc9 and -dff");
run(stringf("techmap -D NO_LUT %s -map +/ecp5/cells_map.v", help_mode ? "[-D ASYNC_PRLD]" : (asyncprld ? "-D ASYNC_PRLD" : "")));
run("opt_expr -undriven -mux_undef");
run("simplemap");

2
techlibs/ice40/synth_ice40.cc
View File

@ -362,7 +362,7 @@ struct SynthIce40Pass : public ScriptPass
run("simplemap t:$dff");
}
if ((abc9 && dff) || help_mode)
run("zinit -all", "(-abc9 and -dff only)");
run("zinit -all t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "(only if -abc9 and -dff");
run("techmap -map +/ice40/ff_map.v");
run("opt_expr -mux_undef");
run("simplemap");

2
techlibs/xilinx/Makefile.inc
View File

@ -54,8 +54,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc5v_dsp_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_dsp_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_dsp_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_unmap.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_model.v))
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))

432
techlibs/xilinx/abc9_map.v
View File

@ -1,432 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* 2019 Eddie Hung <eddie@fpgeh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// The following techmapping rules are intended to be run (with -max_iter 1)
// before invoking the `abc9` pass in order to transform the design into
// a format that it understands.
// Attach a (combinatorial) black-box onto the output
// of thes LUTRAM primitives to capture their
// asynchronous read behaviour
module RAM32X1D (
output DPO, SPO,
(* techmap_autopurge *) input D,
(* techmap_autopurge *) input WCLK,
(* techmap_autopurge *) input WE,
(* techmap_autopurge *) input A0, A1, A2, A3, A4,
(* techmap_autopurge *) input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
parameter INIT = 32'h0;
parameter IS_WCLK_INVERTED = 1'b0;
wire $DPO, $SPO;
RAM32X1D #(
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) _TECHMAP_REPLACE_ (
.DPO($DPO), .SPO($SPO),
.D(D), .WCLK(WCLK), .WE(WE),
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
);
$__ABC9_RAM6 spo (.A($SPO), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO));
$__ABC9_RAM6 dpo (.A($DPO), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
endmodule
module RAM64X1D (
output DPO, SPO,
(* techmap_autopurge *) input D,
(* techmap_autopurge *) input WCLK,
(* techmap_autopurge *) input WE,
(* techmap_autopurge *) input A0, A1, A2, A3, A4, A5,
(* techmap_autopurge *) input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
parameter INIT = 64'h0;
parameter IS_WCLK_INVERTED = 1'b0;
wire $DPO, $SPO;
RAM64X1D #(
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) _TECHMAP_REPLACE_ (
.DPO($DPO), .SPO($SPO),
.D(D), .WCLK(WCLK), .WE(WE),
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
);
$__ABC9_RAM6 spo (.A($SPO), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO));
$__ABC9_RAM6 dpo (.A($DPO), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
endmodule
module RAM128X1D (
output DPO, SPO,
(* techmap_autopurge *) input D,
(* techmap_autopurge *) input WCLK,
(* techmap_autopurge *) input WE,
(* techmap_autopurge *) input [6:0] A, DPRA
);
parameter INIT = 128'h0;
parameter IS_WCLK_INVERTED = 1'b0;
wire $DPO, $SPO;
RAM128X1D #(
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) _TECHMAP_REPLACE_ (
.DPO($DPO), .SPO($SPO),
.D(D), .WCLK(WCLK), .WE(WE),
.A(A),
.DPRA(DPRA)
);
$__ABC9_RAM7 spo (.A($SPO), .S(A), .Y(SPO));
$__ABC9_RAM7 dpo (.A($DPO), .S(DPRA), .Y(DPO));
endmodule
module RAM32M (
output [1:0] DOA,
output [1:0] DOB,
output [1:0] DOC,
output [1:0] DOD,
(* techmap_autopurge *) input [4:0] ADDRA,
(* techmap_autopurge *) input [4:0] ADDRB,
(* techmap_autopurge *) input [4:0] ADDRC,
(* techmap_autopurge *) input [4:0] ADDRD,
(* techmap_autopurge *) input [1:0] DIA,
(* techmap_autopurge *) input [1:0] DIB,
(* techmap_autopurge *) input [1:0] DIC,
(* techmap_autopurge *) input [1:0] DID,
(* techmap_autopurge *) input WCLK,
(* techmap_autopurge *) input WE
);
parameter [63:0] INIT_A = 64'h0000000000000000;
parameter [63:0] INIT_B = 64'h0000000000000000;
parameter [63:0] INIT_C = 64'h0000000000000000;
parameter [63:0] INIT_D = 64'h0000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
wire [1:0] $DOA, $DOB, $DOC, $DOD;
RAM32M #(
.INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) _TECHMAP_REPLACE_ (
.DOA($DOA), .DOB($DOB), .DOC($DOC), .DOD($DOD),
.WCLK(WCLK), .WE(WE),
.ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
.DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
);
$__ABC9_RAM6 doa0 (.A($DOA[0]), .S({1'b1, ADDRA}), .Y(DOA[0]));
$__ABC9_RAM6 doa1 (.A($DOA[1]), .S({1'b1, ADDRA}), .Y(DOA[1]));
$__ABC9_RAM6 dob0 (.A($DOB[0]), .S({1'b1, ADDRB}), .Y(DOB[0]));
$__ABC9_RAM6 dob1 (.A($DOB[1]), .S({1'b1, ADDRB}), .Y(DOB[1]));
$__ABC9_RAM6 doc0 (.A($DOC[0]), .S({1'b1, ADDRC}), .Y(DOC[0]));
$__ABC9_RAM6 doc1 (.A($DOC[1]), .S({1'b1, ADDRC}), .Y(DOC[1]));
$__ABC9_RAM6 dod0 (.A($DOD[0]), .S({1'b1, ADDRD}), .Y(DOD[0]));
$__ABC9_RAM6 dod1 (.A($DOD[1]), .S({1'b1, ADDRD}), .Y(DOD[1]));
endmodule
module RAM64M (
output DOA,
output DOB,
output DOC,
output DOD,
(* techmap_autopurge *) input [5:0] ADDRA,
(* techmap_autopurge *) input [5:0] ADDRB,
(* techmap_autopurge *) input [5:0] ADDRC,
(* techmap_autopurge *) input [5:0] ADDRD,
(* techmap_autopurge *) input DIA,
(* techmap_autopurge *) input DIB,
(* techmap_autopurge *) input DIC,
(* techmap_autopurge *) input DID,
(* techmap_autopurge *) input WCLK,
(* techmap_autopurge *) input WE
);
parameter [63:0] INIT_A = 64'h0000000000000000;
parameter [63:0] INIT_B = 64'h0000000000000000;
parameter [63:0] INIT_C = 64'h0000000000000000;
parameter [63:0] INIT_D = 64'h0000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
wire $DOA, $DOB, $DOC, $DOD;
RAM64M #(
.INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) _TECHMAP_REPLACE_ (
.DOA($DOA), .DOB($DOB), .DOC($DOC), .DOD($DOD),
.WCLK(WCLK), .WE(WE),
.ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
.DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
);
$__ABC9_RAM6 doa (.A($DOA), .S(ADDRA), .Y(DOA));
$__ABC9_RAM6 dob (.A($DOB), .S(ADDRB), .Y(DOB));
$__ABC9_RAM6 doc (.A($DOC), .S(ADDRC), .Y(DOC));
$__ABC9_RAM6 dod (.A($DOD), .S(ADDRD), .Y(DOD));
endmodule
module SRL16 (
output Q,
(* techmap_autopurge *) input A0, A1, A2, A3, CLK, D
);
parameter [15:0] INIT = 16'h0000;
wire $Q;
SRL16 #(
.INIT(INIT),
) _TECHMAP_REPLACE_ (
.Q($Q),
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CLK(CLK), .D(D)
);
$__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
endmodule
module SRL16E (
output Q,
(* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D
);
parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
wire $Q;
SRL16E #(
.INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
) _TECHMAP_REPLACE_ (
.Q($Q),
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
);
$__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
endmodule
module SRLC16 (
output Q, Q15,
(* techmap_autopurge *) input A0, A1, A2, A3, CLK, D
);
parameter [15:0] INIT = 16'h0000;
wire $Q;
SRLC16 #(
.INIT(INIT),
) _TECHMAP_REPLACE_ (
.Q($Q), .Q(Q15),
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CLK(CLK), .D(D)
);
$__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
endmodule
module SRLC16E (
output Q, Q15,
(* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D
);
parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
wire $Q;
SRLC16E #(
.INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
) _TECHMAP_REPLACE_ (
.Q($Q), .Q(Q15),
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
);
$__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
endmodule
module SRLC32E (
output Q,
output Q31,
(* techmap_autopurge *) input [4:0] A,
(* techmap_autopurge *) input CE, CLK, D
);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
wire $Q;
SRLC32E #(
.INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
) _TECHMAP_REPLACE_ (
.Q($Q), .Q31(Q31),
.A(A), .CE(CE), .CLK(CLK), .D(D)
);
$__ABC9_RAM6 q (.A($Q), .S({1'b1, A}), .Y(Q));
endmodule
module DSP48E1 (
(* techmap_autopurge *) output [29:0] ACOUT,
(* techmap_autopurge *) output [17:0] BCOUT,
(* techmap_autopurge *) output reg CARRYCASCOUT,
(* techmap_autopurge *) output reg [3:0] CARRYOUT,
(* techmap_autopurge *) output reg MULTSIGNOUT,
(* techmap_autopurge *) output OVERFLOW,
(* techmap_autopurge *) output reg signed [47:0] P,
(* techmap_autopurge *) output PATTERNBDETECT,
(* techmap_autopurge *) output PATTERNDETECT,
(* techmap_autopurge *) output [47:0] PCOUT,
(* techmap_autopurge *) output UNDERFLOW,
(* techmap_autopurge *) input signed [29:0] A,
(* techmap_autopurge *) input [29:0] ACIN,
(* techmap_autopurge *) input [3:0] ALUMODE,
(* techmap_autopurge *) input signed [17:0] B,
(* techmap_autopurge *) input [17:0] BCIN,
(* techmap_autopurge *) input [47:0] C,
(* techmap_autopurge *) input CARRYCASCIN,
(* techmap_autopurge *) input CARRYIN,
(* techmap_autopurge *) input [2:0] CARRYINSEL,
(* techmap_autopurge *) input CEA1,
(* techmap_autopurge *) input CEA2,
(* techmap_autopurge *) input CEAD,
(* techmap_autopurge *) input CEALUMODE,
(* techmap_autopurge *) input CEB1,
(* techmap_autopurge *) input CEB2,
(* techmap_autopurge *) input CEC,
(* techmap_autopurge *) input CECARRYIN,
(* techmap_autopurge *) input CECTRL,
(* techmap_autopurge *) input CED,
(* techmap_autopurge *) input CEINMODE,
(* techmap_autopurge *) input CEM,
(* techmap_autopurge *) input CEP,
(* techmap_autopurge *) input CLK,
(* techmap_autopurge *) input [24:0] D,
(* techmap_autopurge *) input [4:0] INMODE,
(* techmap_autopurge *) input MULTSIGNIN,
(* techmap_autopurge *) input [6:0] OPMODE,
(* techmap_autopurge *) input [47:0] PCIN,
(* techmap_autopurge *) input RSTA,
(* techmap_autopurge *) input RSTALLCARRYIN,
(* techmap_autopurge *) input RSTALUMODE,
(* techmap_autopurge *) input RSTB,
(* techmap_autopurge *) input RSTC,
(* techmap_autopurge *) input RSTCTRL,
(* techmap_autopurge *) input RSTD,
(* techmap_autopurge *) input RSTINMODE,
(* techmap_autopurge *) input RSTM,
(* techmap_autopurge *) input RSTP
);
parameter integer ACASCREG = 1;
parameter integer ADREG = 1;
parameter integer ALUMODEREG = 1;
parameter integer AREG = 1;
parameter AUTORESET_PATDET = "NO_RESET";
parameter A_INPUT = "DIRECT";
parameter integer BCASCREG = 1;
parameter integer BREG = 1;
parameter B_INPUT = "DIRECT";
parameter integer CARRYINREG = 1;
parameter integer CARRYINSELREG = 1;
parameter integer CREG = 1;
parameter integer DREG = 1;
parameter integer INMODEREG = 1;
parameter integer MREG = 1;
parameter integer OPMODEREG = 1;
parameter integer PREG = 1;
parameter SEL_MASK = "MASK";
parameter SEL_PATTERN = "PATTERN";
parameter USE_DPORT = "FALSE";
parameter USE_MULT = "MULTIPLY";
parameter USE_PATTERN_DETECT = "NO_PATDET";
parameter USE_SIMD = "ONE48";
parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
parameter [47:0] PATTERN = 48'h000000000000;
parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
parameter [4:0] IS_INMODE_INVERTED = 5'b0;
parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
wire [47:0] $P, $PCOUT;
DSP48E1 #(
.ACASCREG(ACASCREG),
.ADREG(ADREG),
.ALUMODEREG(ALUMODEREG),
.AREG(AREG),
.AUTORESET_PATDET(AUTORESET_PATDET),
.A_INPUT(A_INPUT),
.BCASCREG(BCASCREG),
.BREG(BREG),
.B_INPUT(B_INPUT),
.CARRYINREG(CARRYINREG),
.CARRYINSELREG(CARRYINSELREG),
.CREG(CREG),
.DREG(DREG),
.INMODEREG(INMODEREG),
.MREG(MREG),
.OPMODEREG(OPMODEREG),
.PREG(PREG),
.SEL_MASK(SEL_MASK),
.SEL_PATTERN(SEL_PATTERN),
.USE_DPORT(USE_DPORT),
.USE_MULT(USE_MULT),
.USE_PATTERN_DETECT(USE_PATTERN_DETECT),
.USE_SIMD(USE_SIMD),
.MASK(MASK),
.PATTERN(PATTERN),
.IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
.IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
.IS_CLK_INVERTED(IS_CLK_INVERTED),
.IS_INMODE_INVERTED(IS_INMODE_INVERTED),
.IS_OPMODE_INVERTED(IS_OPMODE_INVERTED)
) _TECHMAP_REPLACE_ (
.ACOUT(ACOUT),
.BCOUT(BCOUT),
.CARRYCASCOUT(CARRYCASCOUT),
.CARRYOUT(CARRYOUT),
.MULTSIGNOUT(MULTSIGNOUT),
.OVERFLOW(OVERFLOW),
.P($P),
.PATTERNBDETECT(PATTERNBDETECT),
.PATTERNDETECT(PATTERNDETECT),
.PCOUT($PCOUT),
.UNDERFLOW(UNDERFLOW),
.A(A),
.ACIN(ACIN),
.ALUMODE(ALUMODE),
.B(B),
.BCIN(BCIN),
.C(C),
.CARRYCASCIN(CARRYCASCIN),
.CARRYIN(CARRYIN),
.CARRYINSEL(CARRYINSEL),
.CEA1(CEA1),
.CEA2(CEA2),
.CEAD(CEAD),
.CEALUMODE(CEALUMODE),
.CEB1(CEB1),
.CEB2(CEB2),
.CEC(CEC),
.CECARRYIN(CECARRYIN),
.CECTRL(CECTRL),
.CED(CED),
.CEINMODE(CEINMODE),
.CEM(CEM),
.CEP(CEP),
.CLK(CLK),
.D(D),
.INMODE(INMODE),
.MULTSIGNIN(MULTSIGNIN),
.OPMODE(OPMODE),
.PCIN(PCIN),
.RSTA(RSTA),
.RSTALLCARRYIN(RSTALLCARRYIN),
.RSTALUMODE(RSTALUMODE),
.RSTB(RSTB),
.RSTC(RSTC),
.RSTCTRL(RSTCTRL),
.RSTD(RSTD),
.RSTINMODE(RSTINMODE),
.RSTM(RSTM),
.RSTP(RSTP)
);
$__ABC9_DSP48E1 #(
.ADREG(ADREG),
.AREG(AREG),
.BREG(BREG),
.CREG(CREG),
.DREG(DREG),
.MREG(MREG),
.PREG(PREG),
.USE_DPORT(USE_DPORT),
.USE_MULT(USE_MULT)
) dsp_comb (
.$A(A), .$B(B), .$C(C), .$D(D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
endmodule

171
techlibs/xilinx/abc9_model.v
View File

@ -37,174 +37,3 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
(S1 => O) = 273;
endspecify
endmodule
// Box to emulate async behaviour of FDC*
(* abc9_box, lib_whitebox *)
module \$__ABC9_ASYNC0 (input A, S, output Y);
assign Y = S ? 1'b0 : A;
specify
(A => Y) = 0;
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
(S => Y) = 764;
endspecify
endmodule
// Box to emulate async behaviour of FDP*
(* abc9_box, lib_whitebox *)
module \$__ABC9_ASYNC1 (input A, S, output Y);
assign Y = S ? 1'b1 : A;
specify
(A => Y) = 0;
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
(S => Y) = 764;
endspecify
endmodule
// Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32}
// Necessary since RAMD* and SRL* have both combinatorial (i.e.
// same-cycle read operation) and sequential (write operation
// is only committed on the next clock edge).
// To model the combinatorial path, such cells have to be split
// into comb and seq parts, with this box modelling only the former.
(* abc9_box *)
module \$__ABC9_RAM6 (input A, input [5:0] S, output Y);
specify
(A => Y) = 0;
(S[0] => Y) = 642;
(S[1] => Y) = 631;
(S[2] => Y) = 472;
(S[3] => Y) = 407;
(S[4] => Y) = 238;
(S[5] => Y) = 127;
endspecify
endmodule
// Box to emulate comb/seq behaviour of RAM128
(* abc9_box *)
module \$__ABC9_RAM7 (input A, input [6:0] S, output Y);
specify
(A => Y) = 0;
// https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L867
(S[0] => Y) = 642 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(S[1] => Y) = 631 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(S[2] => Y) = 472 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(S[3] => Y) = 407 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(S[4] => Y) = 238 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(S[5] => Y) = 127 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(S[6] => Y) = 0 + 296 /* to select F7BMUX */ + 174 /* CMUX */;
endspecify
endmodule
// Boxes used to represent the comb behaviour of DSP48E1
(* abc9_box *)
module $__ABC9_DSP48E1 (
input [29:0] $A,
input [17:0] $B,
input [47:0] $C,
input [24:0] $D,
input [47:0] $P,
input [47:0] $PCIN,
input [47:0] $PCOUT,
output [47:0] P,
output [47:0] PCOUT
);
parameter integer ADREG = 1;
parameter integer AREG = 1;
parameter integer BREG = 1;
parameter integer CREG = 1;
parameter integer DREG = 1;
parameter integer MREG = 1;
parameter integer PREG = 1;
parameter USE_DPORT = "FALSE";
parameter USE_MULT = "MULTIPLY";
function integer \A.P.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.P.comb = 2823;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.P.comb = 3806;
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.P.comb = 1523;
end
endfunction
function integer \A.PCOUT.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.PCOUT.comb = 2970;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.PCOUT.comb = 3954;
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.PCOUT.comb = 1671;
end
endfunction
function integer \B.P.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.P.comb = 2690;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.P.comb = 2690;
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.P.comb = 1509;
end
endfunction
function integer \B.PCOUT.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.PCOUT.comb = 2838;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.PCOUT.comb = 2838;
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.PCOUT.comb = 1658;
end
endfunction
function integer \C.P.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.P.comb = 1325;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.P.comb = 1325;
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.P.comb = 1325;
end
endfunction
function integer \C.PCOUT.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.PCOUT.comb = 1474;
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474;
end
endfunction
function integer \D.P.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.P.comb = 3717;
end
endfunction
function integer \D.PCOUT.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.PCOUT.comb = 3700;
end
endfunction
specify
($P *> P) = 0;
($PCOUT *> PCOUT) = 0;
endspecify
// Identical comb delays to DSP48E1 in cells_sim.v
generate
if (PREG == 0 && MREG == 0 && AREG == 0 && ADREG == 0)
specify
($A *> P) = \A.P.comb ();
($A *> PCOUT) = \A.PCOUT.comb ();
endspecify
if (PREG == 0 && MREG == 0 && BREG == 0)
specify
($B *> P) = \B.P.comb ();
($B *> PCOUT) = \B.PCOUT.comb ();
endspecify
if (PREG == 0 && CREG == 0)
specify
($C *> P) = \C.P.comb ();
($C *> PCOUT) = \C.PCOUT.comb ();
endspecify
if (PREG == 0 && MREG == 0 && ADREG == 0 && DREG == 0)
specify
($D *> P) = \D.P.comb ();
($D *> PCOUT) = \D.PCOUT.comb ();
endspecify
if (PREG == 0)
specify
($PCIN *> P) = 1107;
($PCIN *> PCOUT) = 1255;
endspecify
endgenerate
endmodule

57
techlibs/xilinx/abc9_unmap.v
View File

@ -1,57 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* 2019 Eddie Hung <eddie@fpgeh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// ============================================================================
(* techmap_celltype = "$__ABC9_ASYNC0 $__ABC9_ASYNC1" *)
module $__ABC9_ASYNC01(input A, S, output Y);
assign Y = A;
endmodule
module $__ABC9_RAM6(input A, input [5:0] S, output Y);
assign Y = A;
endmodule
module $__ABC9_RAM7(input A, input [6:0] S, output Y);
assign Y = A;
endmodule
module $__ABC9_DSP48E1(
input [29:0] $A,
input [17:0] $B,
input [47:0] $C,
input [24:0] $D,
input [47:0] $P,
input [47:0] $PCIN,
input [47:0] $PCOUT,
output [47:0] P,
output [47:0] PCOUT
);
parameter integer ADREG = 1;
parameter integer AREG = 1;
parameter integer BREG = 1;
parameter integer CREG = 1;
parameter integer DREG = 1;
parameter integer MREG = 1;
parameter integer PREG = 1;
parameter USE_DPORT = "FALSE";
parameter USE_MULT = "MULTIPLY";
assign P = $P, PCOUT = $PCOUT;
endmodule

222
techlibs/xilinx/cells_sim.v
View File

@ -524,10 +524,10 @@ module FDRE (
$setup(R , posedge C &&& !IS_C_INVERTED, 404);
$setup(R , negedge C &&& IS_C_INVERTED, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
if (!IS_C_INVERTED && R ^ IS_R_INVERTED) (posedge C => (Q : 1'b0)) = 303;
if ( IS_C_INVERTED && R ^ IS_R_INVERTED) (negedge C => (Q : 1'b0)) = 303;
if (!IS_C_INVERTED && R ~^ IS_R_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if ( IS_C_INVERTED && R ~^ IS_R_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if (!IS_C_INVERTED && R != IS_R_INVERTED) (posedge C => (Q : 1'b0)) = 303;
if ( IS_C_INVERTED && R != IS_R_INVERTED) (negedge C => (Q : 1'b0)) = 303;
if (!IS_C_INVERTED && R == IS_R_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if ( IS_C_INVERTED && R == IS_R_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
endspecify
endmodule
@ -589,10 +589,10 @@ module FDSE (
$setup(S , posedge C &&& !IS_C_INVERTED, 404);
$setup(S , negedge C &&& IS_C_INVERTED, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
if (!IS_C_INVERTED && S ^ IS_S_INVERTED) (posedge C => (Q : 1'b1)) = 303;
if ( IS_C_INVERTED && S ^ IS_S_INVERTED) (negedge C => (Q : 1'b1)) = 303;
if (!IS_C_INVERTED && S ~^ IS_S_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if ( IS_C_INVERTED && S ~^ IS_S_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if (!IS_C_INVERTED && S != IS_S_INVERTED) (posedge C => (Q : 1'b1)) = 303;
if ( IS_C_INVERTED && S != IS_S_INVERTED) (negedge C => (Q : 1'b1)) = 303;
if (!IS_C_INVERTED && S == IS_S_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if ( IS_C_INVERTED && S == IS_S_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
endspecify
endmodule
@ -656,6 +656,7 @@ module FDRSE (
Q <= d;
endmodule
(* abc9_box, lib_whitebox *)
module FDCE (
output reg Q,
(* clkbuf_sink *)
@ -691,13 +692,15 @@ module FDCE (
$setup(CLR, posedge C &&& !IS_C_INVERTED, 404);
$setup(CLR, negedge C &&& IS_C_INVERTED, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
//if (!IS_CLR_INVERTED) (posedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0
//if ( IS_CLR_INVERTED) (negedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0
if (!IS_C_INVERTED && CLR ~^ IS_CLR_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if ( IS_C_INVERTED && CLR ~^ IS_CLR_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if (IS_CLR_INVERTED != CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
if (!IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if ( IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module FDCE_1 (
output reg Q,
(* clkbuf_sink *)
@ -717,11 +720,14 @@ module FDCE_1 (
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(CLR, negedge C, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
//(posedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0
if (CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
if (!CLR && CE) (negedge C => (Q : D)) = 303;
endspecify
endmodule
//(* abc9_box, lib_whitebox *)
module FDPE (
output reg Q,
(* clkbuf_sink *)
@ -756,13 +762,15 @@ module FDPE (
$setup(PRE, posedge C &&& !IS_C_INVERTED, 404);
$setup(PRE, negedge C &&& IS_C_INVERTED, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
//if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
//if ( IS_PRE_INVERTED) (negedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
if (!IS_C_INVERTED && PRE ~^ IS_PRE_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if ( IS_C_INVERTED && PRE ~^ IS_PRE_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if (IS_PRE_INVERTED != PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
if (!IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if ( IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module FDPE_1 (
output reg Q,
(* clkbuf_sink *)
@ -782,8 +790,9 @@ module FDPE_1 (
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(PRE, negedge C, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
//if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
//if (IS_PRE_INVERTED) (negedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
if (PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
if (!PRE && CE) (negedge C => (Q : D)) = 303;
endspecify
endmodule
@ -1395,6 +1404,7 @@ module RAM16X1D_1 (
always @(negedge clk) if (WE) mem[a] <= D;
endmodule
(* abc9_box, lib_whitebox *)
module RAM32X1D (
output DPO, SPO,
input D,
@ -1441,15 +1451,15 @@ module RAM32X1D (
if (!IS_WCLK_INVERTED) (posedge WCLK => (DPO : 1'bx)) = 1153;
if ( IS_WCLK_INVERTED) (posedge WCLK => (SPO : D)) = 1153;
if ( IS_WCLK_INVERTED) (negedge WCLK => (DPO : 1'bx)) = 1153;
// Captured by $__ABC9_RAM6
//({A0,DPRA0} => {SPO,DPO}) = 642;
//({A1,DPRA1} => {SPO,DPO}) = 631;
//({A2,DPRA2} => {SPO,DPO}) = 472;
//({A3,DPRA3} => {SPO,DPO}) = 407;
//({A4,DPRA4} => {SPO,DPO}) = 238;
(A0 => SPO) = 642; (DPRA0 => DPO) = 642;
(A1 => SPO) = 632; (DPRA1 => DPO) = 631;
(A2 => SPO) = 472; (DPRA2 => DPO) = 472;
(A3 => SPO) = 407; (DPRA3 => DPO) = 407;
(A4 => SPO) = 238; (DPRA4 => DPO) = 238;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module RAM32X1D_1 (
output DPO, SPO,
input D,
@ -1491,15 +1501,15 @@ module RAM32X1D_1 (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
if (WE) (negedge WCLK => (SPO : D)) = 1153;
if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153;
// Captured by $__ABC9_RAM6
//({A0,DPRA0} => {SPO,DPO}) = 642;
//({A1,DPRA1} => {SPO,DPO}) = 631;
//({A2,DPRA2} => {SPO,DPO}) = 472;
//({A3,DPRA3} => {SPO,DPO}) = 407;
//({A4,DPRA4} => {SPO,DPO}) = 238;
(A0 => SPO) = 642; (DPRA0 => DPO) = 642;
(A1 => SPO) = 632; (DPRA1 => DPO) = 631;
(A2 => SPO) = 472; (DPRA2 => DPO) = 472;
(A3 => SPO) = 407; (DPRA3 => DPO) = 407;
(A4 => SPO) = 238; (DPRA4 => DPO) = 238;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module RAM64X1D (
output DPO, SPO,
input D,
@ -1549,13 +1559,12 @@ module RAM64X1D (
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DPO : 1'bx)) = 1153;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (SPO : D)) = 1153;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153;
// Captured by $__ABC9_RAM6
//({A0,DPRA0} => {SPO,DPO}) = 642;
//({A1,DPRA1} => {SPO,DPO}) = 631;
//({A2,DPRA2} => {SPO,DPO}) = 472;
//({A3,DPRA3} => {SPO,DPO}) = 407;
//({A4,DPRA4} => {SPO,DPO}) = 238;
//({A5,DPRA5} => {SPO,DPO}) = 127;
(A0 => SPO) = 642; (DPRA0 => DPO) = 642;
(A1 => SPO) = 632; (DPRA1 => DPO) = 631;
(A2 => SPO) = 472; (DPRA2 => DPO) = 472;
(A3 => SPO) = 407; (DPRA3 => DPO) = 407;
(A4 => SPO) = 238; (DPRA4 => DPO) = 238;
(A5 => SPO) = 127; (DPRA5 => DPO) = 127;
endspecify
endmodule
@ -1598,9 +1607,16 @@ module RAM64X1D_1 (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
if (WE) (negedge WCLK => (SPO : D)) = 1153;
if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153;
(A0 => SPO) = 642; (DPRA0 => DPO) = 642;
(A1 => SPO) = 632; (DPRA1 => DPO) = 631;
(A2 => SPO) = 472; (DPRA2 => DPO) = 472;
(A3 => SPO) = 407; (DPRA3 => DPO) = 407;
(A4 => SPO) = 238; (DPRA4 => DPO) = 238;
(A5 => SPO) = 127; (DPRA5 => DPO) = 127;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module RAM128X1D (
output DPO, SPO,
input D,
@ -1645,21 +1661,20 @@ module RAM128X1D (
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D)) = 1153 + 217 /* to cross F7AMUX */ + 175 /* AMUX */;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
`endif
// Captured by $__ABC9_RAM7
//(A[0] => SPO) = 642 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
//(A[1] => SPO) = 631 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
//(A[2] => SPO) = 472 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
//(A[3] => SPO) = 407 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
//(A[4] => SPO) = 238 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
//(A[5] => SPO) = 127 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
//(A[6] => SPO) = 0 + 276 /* to select F7AMUX */ + 175 /* AMUX */;
//(DPRA[0] => DPO) = 642 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
//(DPRA[1] => DPO) = 631 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
//(DPRA[2] => DPO) = 472 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
//(DPRA[3] => DPO) = 407 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
//(DPRA[4] => DPO) = 238 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
//(DPRA[5] => DPO) = 127 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
//(DPRA[6] => DPO) = 0 + 296 /* to select MUXF7 */ + 174 /* CMUX */;
(A[0] => SPO) = 642 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
(A[1] => SPO) = 631 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
(A[2] => SPO) = 472 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
(A[3] => SPO) = 407 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
(A[4] => SPO) = 238 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
(A[5] => SPO) = 127 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
(A[6] => SPO) = 0 + 276 /* to select F7AMUX */ + 175 /* AMUX */;
(DPRA[0] => DPO) = 642 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
(DPRA[1] => DPO) = 631 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
(DPRA[2] => DPO) = 472 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
(DPRA[3] => DPO) = 407 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
(DPRA[4] => DPO) = 238 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
(DPRA[5] => DPO) = 127 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
(DPRA[6] => DPO) = 0 + 296 /* to select MUXF7 */ + 174 /* CMUX */;
endspecify
endmodule
@ -1683,6 +1698,7 @@ endmodule
// Multi port.
(* abc9_box, lib_whitebox *)
module RAM32M (
output [1:0] DOA,
output [1:0] DOB,
@ -1779,12 +1795,11 @@ module RAM32M (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD[1] : DID[1])) = 1190;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD[1] : DID[1])) = 1190;
// Captured by $__ABC9_RAM6
//({{2{ADDRA[0]}},{2{ADDRB[0]}},{2{ADDRC[0]}},{2{ADDRD[0]}}} => {DOA,DOB,DOC,DOD}) = 642;
//({{2{ADDRA[1]}},{2{ADDRB[1]}},{2{ADDRC[1]}},{2{ADDRD[1]}}} => {DOA,DOB,DOC,DOD}) = 631;
//({{2{ADDRA[2]}},{2{ADDRB[2]}},{2{ADDRC[2]}},{2{ADDRD[2]}}} => {DOA,DOB,DOC,DOD}) = 472;
//({{2{ADDRA[3]}},{2{ADDRB[3]}},{2{ADDRC[3]}},{2{ADDRD[3]}}} => {DOA,DOB,DOC,DOD}) = 407;
//({{2{ADDRA[4]}},{2{ADDRB[4]}},{2{ADDRC[4]}},{2{ADDRD[4]}}} => {DOA,DOB,DOC,DOD}) = 238;
(ADDRA[0] *> DOA) = 642; (ADDRB[0] *> DOB) = 642; (ADDRC[0] *> DOC) = 642; (ADDRD[0] *> DOD) = 642;
(ADDRA[1] *> DOA) = 631; (ADDRB[1] *> DOB) = 631; (ADDRC[1] *> DOC) = 631; (ADDRD[1] *> DOD) = 631;
(ADDRA[2] *> DOA) = 472; (ADDRB[2] *> DOB) = 472; (ADDRC[2] *> DOC) = 472; (ADDRD[2] *> DOD) = 472;
(ADDRA[3] *> DOA) = 407; (ADDRB[3] *> DOB) = 407; (ADDRC[3] *> DOC) = 407; (ADDRD[3] *> DOD) = 407;
(ADDRA[4] *> DOA) = 238; (ADDRB[4] *> DOB) = 238; (ADDRC[4] *> DOC) = 238; (ADDRD[4] *> DOD) = 238;
endspecify
endmodule
@ -1857,6 +1872,7 @@ module RAM32M16 (
end
endmodule
(* abc9_box, lib_whitebox *)
module RAM64M (
output DOA,
output DOB,
@ -1935,12 +1951,11 @@ module RAM64M (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD : DID)) = 1163;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD : DID)) = 1163;
// Captured by $__ABC9_RAM6
//({ADDRA[0],ADDRB[0],ADDRC[0],ADDRD[0]} => {DOA,DOB,DOC,DOD}) = 642;
//({ADDRA[1],ADDRB[1],ADDRC[1],ADDRD[1]} => {DOA,DOB,DOC,DOD}) = 631;
//({ADDRA[2],ADDRB[2],ADDRC[2],ADDRD[2]} => {DOA,DOB,DOC,DOD}) = 472;
//({ADDRA[3],ADDRB[3],ADDRC[3],ADDRD[3]} => {DOA,DOB,DOC,DOD}) = 407;
//({ADDRA[4],ADDRB[4],ADDRC[4],ADDRD[4]} => {DOA,DOB,DOC,DOD}) = 238;
(ADDRA[0] => DOA) = 642; (ADDRB[0] => DOB) = 642; (ADDRC[0] => DOC) = 642; (ADDRD[0] => DOD) = 642;
(ADDRA[1] => DOA) = 631; (ADDRB[1] => DOB) = 631; (ADDRC[1] => DOC) = 631; (ADDRD[1] => DOD) = 631;
(ADDRA[2] => DOA) = 472; (ADDRB[2] => DOB) = 472; (ADDRC[2] => DOC) = 472; (ADDRD[2] => DOD) = 472;
(ADDRA[3] => DOA) = 407; (ADDRB[3] => DOB) = 407; (ADDRC[3] => DOC) = 407; (ADDRD[3] => DOD) = 407;
(ADDRA[4] => DOA) = 238; (ADDRB[4] => DOB) = 238; (ADDRC[4] => DOC) = 238; (ADDRD[4] => DOD) = 238;
endspecify
endmodule
@ -2057,6 +2072,7 @@ endmodule
// Shift registers.
(* abc9_box, lib_whitebox *)
module SRL16 (
output Q,
input A0, A1, A2, A3,
@ -2075,14 +2091,14 @@ module SRL16 (
(posedge CLK => (Q : 1'bx)) = 1472;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
$setup(D , posedge CLK, 173);
// Captured by $__ABC9_RAM6
//(A0 => Q) = 631;
//(A1 => Q) = 472;
//(A2 => Q) = 407;
//(A3 => Q) = 238;
(A0 => Q) = 631;
(A1 => Q) = 472;
(A2 => Q) = 407;
(A3 => Q) = 238;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module SRL16E (
output Q,
input A0, A1, A2, A3, CE,
@ -2108,16 +2124,19 @@ module SRL16E (
$setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173);
$setup(D , negedge CLK &&& IS_CLK_INVERTED, 173);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : D)) = 1472;
if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : D)) = 1472;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1472;
if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1472;
// Captured by $__ABC9_RAM6
//(A0 => Q) = 631;
//(A1 => Q) = 472;
//(A2 => Q) = 407;
//(A3 => Q) = 238;
(A0 => Q) = 631;
(A1 => Q) = 472;
(A2 => Q) = 407;
(A3 => Q) = 238;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module SRLC16 (
output Q,
output Q15,
@ -2134,18 +2153,20 @@ module SRLC16 (
always @(posedge CLK) r <= { r[14:0], D };
specify
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
(posedge CLK => (Q : 1'bx)) = 1472;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
$setup(D , posedge CLK, 173);
// Captured by $__ABC9_RAM6
//(A0 => Q) = 631;
//(A1 => Q) = 472;
//(A2 => Q) = 407;
//(A3 => Q) = 238;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
(posedge CLK => (Q : 1'bx)) = 1472;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
(posedge CLK => (Q15 : 1'bx)) = 1114;
(A0 => Q) = 631;
(A1 => Q) = 472;
(A2 => Q) = 407;
(A3 => Q) = 238;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module SRLC16E (
output Q,
output Q15,
@ -2172,18 +2193,23 @@ module SRLC16E (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
$setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173);
$setup(D , negedge CLK &&& IS_CLK_INVERTED, 173);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE, posedge CLK &&& !IS_CLK_INVERTED, 109);
$setup(CE, negedge CLK &&& IS_CLK_INVERTED, 109);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : D)) = 1472;
if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : D)) = 1472;
// Captured by $__ABC9_RAM6
//(A0 => Q) = 642;
//(A1 => Q) = 631;
//(A2 => Q) = 472;
//(A3 => Q) = 407;
//(A4 => Q) = 238;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q15 : 1'bx)) = 1114;
if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q15 : 1'bx)) = 1114;
(A0 => Q) = 631;
(A1 => Q) = 472;
(A2 => Q) = 407;
(A3 => Q) = 238;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module SRLC32E (
output Q,
output Q31,
@ -2211,18 +2237,20 @@ module SRLC32E (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
$setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173);
$setup(D , negedge CLK &&& IS_CLK_INVERTED, 173);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE, posedge CLK &&& !IS_CLK_INVERTED, 109);
$setup(CE, negedge CLK &&& IS_CLK_INVERTED, 109);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1472;
if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1472;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1114;
if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1114;
// Captured by $__ABC9_RAM6
//(A0 => Q) = 642;
//(A1 => Q) = 631;
//(A2 => Q) = 472;
//(A3 => Q) = 407;
//(A4 => Q) = 238;
if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q31 : 1'bx)) = 1114;
if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q31 : 1'bx)) = 1114;
(A[0] => Q) = 642;
(A[1] => Q) = 631;
(A[2] => Q) = 472;
(A[3] => Q) = 407;
(A[4] => Q) = 238;
endspecify
endmodule
@ -2990,6 +3018,8 @@ endmodule
// Virtex 6, Series 7.
(* abc9_box=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG),
lib_whitebox=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG) *)
module DSP48E1 (
output [29:0] ACOUT,
output [17:0] BCOUT,

4
techlibs/xilinx/synth_xilinx.cc
View File

@ -598,7 +598,7 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("map_ffs", "('-abc9' only)")) {
if (abc9 || help_mode) {
if (dff || help_mode)
run("zinit -all", "('-dff' only)");
run("zinit -all t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "('-dff' only)");
run("techmap -map " + ff_map_file);
}
}
@ -615,7 +615,6 @@ struct SynthXilinxPass : public ScriptPass
if (family != "xc7")
log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
"will use timing for 'xc7' instead.\n", family.c_str());
run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v");
std::string abc9_opts;
std::string k = "synth_xilinx.abc9.W";
@ -630,7 +629,6 @@ struct SynthXilinxPass : public ScriptPass
if (dff)
abc9_opts += " -dff";
run("abc9" + abc9_opts);
run("techmap -map +/xilinx/abc9_unmap.v");
}
else {
std::string abc_opts;

34
tests/arch/xilinx/abc9_dff.ys
View File

@ -46,16 +46,40 @@ FDCE #(.INIT(1)) fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2]));
FDPE #(.INIT(1)) fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3]));
FDRE_1 #(.INIT(1)) fd5(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[4]));
FDSE_1 #(.INIT(1)) fd6(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[5]));
FDCE_1 #(.INIT(1)) fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
FDCE_1 /*#(.INIT(1))*/ fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
FDPE_1 #(.INIT(1)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
endmodule
EOT
logger -expect warning "Module '\$paramod\\FDRE\\INIT=1' contains a \$_DFF_P_ cell .*" 1
logger -expect warning "Module '\$paramod\\FDRE_1\\INIT=1' contains a \$_DFF_N_ cell .*" 1
logger -expect warning "Module 'FDSE' contains a \$_DFF_P_ cell .*" 1
logger -expect warning "Module '\$paramod\\FDSE_1\\INIT=1' contains a \$_DFF_N_ cell .*" 1
logger -expect warning "Module '\$paramod\\FDRE\\INIT=1' contains a \$dff cell .*" 1
logger -expect warning "Module '\$paramod\\FDRE_1\\INIT=1' contains a \$dff cell .*" 1
logger -expect warning "Module 'FDSE' contains a \$dff cell .*" 1
logger -expect warning "Module '\$paramod\\FDSE_1\\INIT=1' contains a \$dff cell .*" 1
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt
select -assert-count 8 t:FD*
design -reset
read_verilog <<EOT
module top(input clk, clr, pre, output reg q0 = 1'b0, output reg q1 = 1'b1);
always @(posedge clk or posedge clr)
if (clr)
q0 <= 1'b0;
else
q0 <= ~q0;
always @(posedge clk or posedge pre)
if (pre)
q1 <= 1'b1;
else
q1 <= ~q1;
endmodule
EOT
proc
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt
select -assert-count 1 t:FDCE
select -assert-count 1 t:FDPE
select -assert-count 2 t:INV
select -assert-count 0 t:FD* t:INV %% t:* %D
logger -expect-no-warnings