mirror of https://github.com/YosysHQ/yosys.git
448 lines
17 KiB
C++
448 lines
17 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* (C) 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// [[CITE]] ABC
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// Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
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// http://www.eecs.berkeley.edu/~alanmi/abc/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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// abc9_exe.cc
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std::string fold_abc9_cmd(std::string str);
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Abc9Pass : public ScriptPass
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{
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Abc9Pass() : ScriptPass("abc9", "use ABC9 for technology mapping") { }
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void on_register() YS_OVERRIDE
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{
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RTLIL::constpad["abc9.script.default"] = "+&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs";
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RTLIL::constpad["abc9.script.default.area"] = "+&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs";
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RTLIL::constpad["abc9.script.default.fast"] = "+&if {C} {W} {D} {R} -v";
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// Based on ABC's &flow
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RTLIL::constpad["abc9.script.flow"] = "+&scorr; &sweep;" \
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"&dch -C 500;" \
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/* Round 1 */ \
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/* Map 1 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
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"&st; &dsdb;" \
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/* Map 2 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
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"&st; &syn2 -m -R 10; &dsdb;" \
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"&blut -a -K 6;" \
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/* Map 3 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
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/* Round 2 */ \
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"&st; &sopb;" \
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/* Map 1 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
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"&st; &dsdb;" \
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/* Map 2 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
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"&st; &syn2 -m -R 10; &dsdb;" \
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"&blut -a -K 6;" \
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/* Map 3 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
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/* Round 3 */ \
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/* Map 1 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
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"&st; &dsdb;" \
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/* Map 2 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
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"&st; &syn2 -m -R 10; &dsdb;" \
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"&blut -a -K 6;" \
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/* Map 3 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;";
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// Based on ABC's &flow2
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RTLIL::constpad["abc9.script.flow2"] = "+&scorr; &sweep;" \
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/* Comm1 */ "&synch2 -K 6 -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
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/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
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"&load; &st; &sopb -R 10 -C 4; " \
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/* Comm3 */ "&synch2 -K 6 -C 500; &if -m "/*"-E 5"*/" {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
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/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save; "\
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"&load";
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// Based on ABC's &flow3
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RTLIL::constpad["abc9.script.flow3"] = "+&scorr; &sweep;" \
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"&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} {R} -v; &save; &load;"\
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"&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} {R} -v; &save; &load;"\
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"&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} {R} -v; &save; &load;"\
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"&mfs";
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}
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" abc9 [options] [selection]\n");
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log("\n");
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log("This script pass performs a sequence of commands to facilitate the use of the ABC\n");
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log("tool [1] for technology mapping of the current design to a target FPGA\n");
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log("architecture. Only fully-selected modules are supported.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -exe <command>\n");
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#ifdef ABCEXTERNAL
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log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
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#else
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log(" use the specified command instead of \"<yosys-bindir>/%syosys-abc\" to execute ABC.\n", proc_program_prefix().c_str());
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#endif
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log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
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log("\n");
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log(" -script <file>\n");
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log(" use the specified ABC script file instead of the default script.\n");
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log("\n");
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log(" if <file> starts with a plus sign (+), then the rest of the filename\n");
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log(" string is interpreted as the command string to be passed to ABC. The\n");
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log(" leading plus sign is removed and all commas (,) in the string are\n");
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log(" replaced with blanks before the string is passed to ABC.\n");
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log("\n");
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log(" if no -script parameter is given, the following scripts are used:\n");
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log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos)).c_str());
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log("\n");
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log(" -fast\n");
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log(" use different default scripts that are slightly faster (at the cost\n");
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log(" of output quality):\n");
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log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)).c_str());
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log("\n");
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log(" -D <picoseconds>\n");
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log(" set delay target. the string {D} in the default scripts above is\n");
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log(" replaced by this option when used, and an empty string otherwise\n");
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log(" (indicating best possible delay).\n");
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log("\n");
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// log(" -S <num>\n");
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// log(" maximum number of LUT inputs shared.\n");
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// log(" (replaces {S} in the default scripts above, default: -S 1)\n");
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// log("\n");
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log(" -lut <width>\n");
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log(" generate netlist using luts of (max) the specified width.\n");
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log("\n");
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log(" -lut <w1>:<w2>\n");
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log(" generate netlist using luts of (max) the specified width <w2>. All\n");
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log(" luts with width <= <w1> have constant cost. for luts larger than <w1>\n");
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log(" the area cost doubles with each additional input bit. the delay cost\n");
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log(" is still constant for all lut widths.\n");
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log("\n");
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log(" -lut <file>\n");
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log(" pass this file with lut library to ABC.\n");
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log("\n");
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log(" -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..\n");
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log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
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log(" 2, 3, .. inputs.\n");
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log("\n");
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log(" -maxlut <width>\n");
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log(" when auto-generating the lut library, discard all luts equal to or\n");
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log(" greater than this size (applicable when neither -lut nor -luts is\n");
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log(" specified).\n");
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log("\n");
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log(" -dff\n");
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log(" also pass $_DFF_[NP]_ cells through to ABC. modules with many clock\n");
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log(" domains are supported and automatically partitioned by ABC.\n");
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log("\n");
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log(" -nocleanup\n");
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log(" when this option is used, the temporary files created by this pass\n");
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log(" are not removed. this is useful for debugging.\n");
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log("\n");
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log(" -showtmp\n");
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log(" print the temp dir name in log. usually this is suppressed so that the\n");
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log(" command output is identical across runs.\n");
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log("\n");
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log(" -box <file>\n");
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log(" pass this file with box library to ABC.\n");
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log("\n");
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log("Note that this is a logic optimization pass within Yosys that is calling ABC\n");
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log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
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log("ABC on logic snippets extracted from your design. You will not get any useful\n");
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log("output when passing an ABC script that writes a file. Instead write your full\n");
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log("design as an XAIGER file with `write_xaiger' and then load that into ABC\n");
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log("externally if you want to use ABC to convert your design into another format.\n");
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log("\n");
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log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
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log("\n");
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help_script();
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log("\n");
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}
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std::stringstream exe_cmd;
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bool dff_mode, cleanup;
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bool lut_mode;
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int maxlut;
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std::string box_file;
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void clear_flags() YS_OVERRIDE
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{
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exe_cmd.str("");
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exe_cmd << "abc9_exe";
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dff_mode = false;
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cleanup = true;
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lut_mode = false;
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maxlut = 0;
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box_file = "";
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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std::string run_from, run_to;
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clear_flags();
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// get arguments from scratchpad first, then override by command arguments
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dff_mode = design->scratchpad_get_bool("abc9.dff", dff_mode);
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cleanup = !design->scratchpad_get_bool("abc9.nocleanup", !cleanup);
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if (design->scratchpad_get_bool("abc9.debug")) {
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cleanup = false;
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exe_cmd << " -showtmp";
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}
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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std::string arg = args[argidx];
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if ((arg == "-exe" || arg == "-script" || arg == "-D" ||
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/*arg == "-S" ||*/ arg == "-lut" || arg == "-luts" ||
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/*arg == "-box" ||*/ arg == "-W") &&
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argidx+1 < args.size()) {
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if (arg == "-lut" || arg == "-luts")
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lut_mode = true;
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exe_cmd << " " << arg << " " << args[++argidx];
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continue;
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}
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if (arg == "-fast" || /* arg == "-dff" || */
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/* arg == "-nocleanup" || */ arg == "-showtmp") {
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exe_cmd << " " << arg;
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continue;
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}
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if (arg == "-dff") {
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dff_mode = true;
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exe_cmd << " " << arg;
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continue;
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}
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if (arg == "-nocleanup") {
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cleanup = false;
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continue;
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}
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if (arg == "-box" && argidx+1 < args.size()) {
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box_file = args[++argidx];
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continue;
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}
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if (arg == "-maxlut" && argidx+1 < args.size()) {
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maxlut = atoi(args[++argidx].c_str());
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continue;
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}
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if (arg == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (maxlut && lut_mode)
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log_cmd_error("abc9 '-maxlut' option only applicable without '-lut' nor '-luts'.\n");
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log_assert(design);
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if (design->selected_modules().empty()) {
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log_warning("No modules selected for ABC9 techmapping.\n");
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return;
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}
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log_header(design, "Executing ABC9 pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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void script() YS_OVERRIDE
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{
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if (check_label("check")) {
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if (help_mode)
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run("abc9_ops -check [-dff]", "(option if -dff)");
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else
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run(stringf("abc9_ops -check %s", dff_mode ? "-dff" : ""));
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}
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if (check_label("map")) {
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if (help_mode)
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run("abc9_ops -prep_hier -prep_bypass [-prep_dff -dff]", "(option if -dff)");
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else
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run(stringf("abc9_ops -prep_hier -prep_bypass %s", dff_mode ? "-prep_dff -dff" : ""));
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if (dff_mode) {
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run("design -copy-to $abc9_map @$abc9_flops", "(only if -dff)");
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run("select -unset $abc9_flops", " (only if -dff)");
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}
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run("design -stash $abc9");
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run("design -load $abc9_map");
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run("proc");
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run("wbflip");
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run("techmap");
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run("opt");
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if (dff_mode) {
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if (!help_mode)
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active_design->scratchpad_unset("abc9_ops.prep_dff_map.did_something");
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run("abc9_ops -prep_dff_map", "(only if -dff)"); // rewrite specify
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bool did_something = help_mode || active_design->scratchpad_get_bool("abc9_ops.prep_dff_map.did_something");
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if (did_something) {
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// select all $_DFF_[NP]_
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// then select all its fanins
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// then select all fanouts of all that
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// lastly remove $_DFF_[NP]_ cells
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run("setattr -set submod \"$abc9_flop\" t:$_DFF_?_ %ci* %co* t:$_DFF_?_ %d");
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run("submod");
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run("setattr -mod -set whitebox 1 -set abc9_flop 1 -set abc9_box 1 *_$abc9_flop");
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run("abc9_ops -prep_dff_unmap");
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run("design -copy-to $abc9 *_$abc9_flop"); // copy submod out
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run("delete *_$abc9_flop");
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if (help_mode) {
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run("foreach module in design");
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run(" rename <module-name>_$abc9_flop _TECHMAP_REPLACE_");
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}
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else {
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// Rename all submod-s to _TECHMAP_REPLACE_ to inherit name + attrs
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for (auto module : active_design->selected_modules()) {
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active_design->selected_active_module = module->name.str();
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if (module->cell(stringf("%s_$abc9_flop", module->name.c_str())))
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run(stringf("rename %s_$abc9_flop _TECHMAP_REPLACE_", module->name.c_str()));
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}
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}
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}
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}
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run("design -stash $abc9_map");
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run("design -load $abc9");
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run("design -delete $abc9");
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run("techmap -wb -max_iter 1 -map %$abc9_map -map +/abc9_map.v");
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run("design -delete $abc9_map");
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}
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if (check_label("pre")) {
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run("read_verilog -icells -lib -specify +/abc9_model.v");
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run("scc -set_attr abc9_scc_id {}");
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if (help_mode)
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run("abc9_ops -mark_scc -prep_delays -prep_xaiger [-dff]", "(option for -dff)");
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else
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run("abc9_ops -mark_scc -prep_delays -prep_xaiger" + std::string(dff_mode ? " -dff" : ""));
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if (help_mode)
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run("abc9_ops -prep_lut <maxlut>", "(skip if -lut or -luts)");
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else if (!lut_mode)
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run(stringf("abc9_ops -prep_lut %d", maxlut));
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if (help_mode)
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run("abc9_ops -prep_box", "(skip if -box)");
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else if (box_file.empty()) {
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run("abc9_ops -prep_box");
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}
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run("design -stash $abc9");
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run("design -load $abc9_holes");
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run("techmap -wb -map %$abc9 -map +/techmap.v");
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run("opt -purge");
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run("aigmap");
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run("design -stash $abc9_holes");
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run("design -load $abc9");
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run("design -delete $abc9");
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}
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if (check_label("exe")) {
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run("aigmap");
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if (help_mode) {
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run("foreach module in selection");
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run(" abc9_ops -write_lut <abc-temp-dir>/input.lut", "(skip if '-lut' or '-luts')");
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run(" abc9_ops -write_box <abc-temp-dir>/input.box", "(skip if '-box')");
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run(" write_xaiger -map <abc-temp-dir>/input.sym [-dff] <abc-temp-dir>/input.xaig");
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run(" abc9_exe [options] -cwd <abc-temp-dir> -lut [<abc-temp-dir>/input.lut] -box [<abc-temp-dir>/input.box]");
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run(" read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig");
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run(" abc9_ops -reintegrate [-dff]");
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}
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else {
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auto selected_modules = active_design->selected_modules();
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active_design->selection_stack.emplace_back(false);
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for (auto mod : selected_modules) {
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if (mod->processes.size() > 0) {
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log("Skipping module %s as it contains processes.\n", log_id(mod));
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continue;
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}
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log_push();
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active_design->selection().select(mod);
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if (!active_design->selected_whole_module(mod))
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log_error("Can't handle partially selected module %s!\n", log_id(mod));
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std::string tempdir_name = "/tmp/" + proc_program_prefix() + "yosys-abc-XXXXXX";
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if (!cleanup)
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tempdir_name[0] = tempdir_name[4] = '_';
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tempdir_name = make_temp_dir(tempdir_name);
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if (!lut_mode)
|
|
run_nocheck(stringf("abc9_ops -write_lut %s/input.lut", tempdir_name.c_str()));
|
|
if (box_file.empty())
|
|
run_nocheck(stringf("abc9_ops -write_box %s/input.box", tempdir_name.c_str()));
|
|
run_nocheck(stringf("write_xaiger -map %s/input.sym %s %s/input.xaig", tempdir_name.c_str(), dff_mode ? "-dff" : "", tempdir_name.c_str()));
|
|
|
|
int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs");
|
|
|
|
log("Extracted %d AND gates and %d wires from module `%s' to a netlist network with %d inputs and %d outputs.\n",
|
|
active_design->scratchpad_get_int("write_xaiger.num_ands"),
|
|
active_design->scratchpad_get_int("write_xaiger.num_wires"),
|
|
log_id(mod),
|
|
active_design->scratchpad_get_int("write_xaiger.num_inputs"),
|
|
num_outputs);
|
|
if (num_outputs) {
|
|
std::string abc9_exe_cmd;
|
|
abc9_exe_cmd += stringf("%s -cwd %s", exe_cmd.str().c_str(), tempdir_name.c_str());
|
|
if (!lut_mode)
|
|
abc9_exe_cmd += stringf(" -lut %s/input.lut", tempdir_name.c_str());
|
|
if (box_file.empty())
|
|
abc9_exe_cmd += stringf(" -box %s/input.box", tempdir_name.c_str());
|
|
else
|
|
abc9_exe_cmd += stringf(" -box %s", box_file.c_str());
|
|
run_nocheck(abc9_exe_cmd);
|
|
run_nocheck(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod), tempdir_name.c_str(), tempdir_name.c_str()));
|
|
run_nocheck(stringf("abc9_ops -reintegrate %s", dff_mode ? "-dff" : ""));
|
|
}
|
|
else
|
|
log("Don't call ABC as there is nothing to map.\n");
|
|
|
|
if (cleanup) {
|
|
log("Removing temp directory.\n");
|
|
remove_directory(tempdir_name);
|
|
}
|
|
mod->check();
|
|
active_design->selection().selected_modules.clear();
|
|
log_pop();
|
|
}
|
|
|
|
active_design->selection_stack.pop_back();
|
|
}
|
|
}
|
|
|
|
if (check_label("unmap")) {
|
|
run("techmap -wb -map %$abc9_unmap -map +/abc9_unmap.v"); // techmap user design from submod back to original cell
|
|
// ($_DFF_[NP]_ already shorted by -reintegrate)
|
|
run("design -delete $abc9_unmap");
|
|
if (saved_designs.count("$abc9_holes") || help_mode)
|
|
run("design -delete $abc9_holes");
|
|
}
|
|
}
|
|
} Abc9Pass;
|
|
|
|
PRIVATE_NAMESPACE_END
|