mirror of https://github.com/YosysHQ/yosys.git
opt_expr: more fixes for $xor/$xnor
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@ -156,13 +156,27 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
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int group_idx = GRP_DYN;
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RTLIL::SigBit bit_a = bits_a[i], bit_b = bits_b[i];
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if (cell->type == ID($or) && (bit_a == RTLIL::State::S1 || bit_b == RTLIL::State::S1))
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bit_a = bit_b = RTLIL::State::S1;
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if (cell->type == ID($or)) {
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if (bit_a == RTLIL::State::S1 || bit_b == RTLIL::State::S1)
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bit_a = bit_b = RTLIL::State::S1;
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}
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else if (cell->type == ID($and)) {
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if (bit_a == RTLIL::State::S0 || bit_b == RTLIL::State::S0)
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bit_a = bit_b = RTLIL::State::S0;
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}
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else if (!keepdc) {
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if (cell->type == ID($xor)) {
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if (bit_a == bit_b)
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bit_a = bit_b = RTLIL::State::S0;
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}
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else if (cell->type == ID($xnor)) {
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if (bit_a == bit_b)
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bit_a = bit_b = RTLIL::State::S1; // For consistency with gate-level which does $xnor -> $_XOR_ + $_NOT_
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}
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}
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if (cell->type == ID($and) && (bit_a == RTLIL::State::S0 || bit_b == RTLIL::State::S0))
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bit_a = bit_b = RTLIL::State::S0;
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if (!keepdc || (bit_a != State::Sx && bit_a != State::Sz && bit_a != State::Sx && bit_a != State::Sx)) {
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bool def = (bit_a != State::Sx && bit_a != State::Sz && bit_b != State::Sx && bit_b != State::Sx);
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if (def || !keepdc) {
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if (bit_a.wire == NULL && bit_b.wire == NULL)
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group_idx = GRP_CONST_AB;
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else if (bit_a.wire == NULL)
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@ -202,43 +216,56 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
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}
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if (cell->type.in(ID($and), ID($or)) && i == GRP_CONST_A) {
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if (cell->type == ID($and))
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new_a.replace(dict<SigBit,SigBit>{{State::Sx, State::S0}, {State::Sz, State::S0}}, &new_b);
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else if (cell->type == ID($or))
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new_a.replace(dict<SigBit,SigBit>{{State::Sx, State::S1}, {State::Sz, State::S1}}, &new_b);
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else log_abort();
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if (!keepdc) {
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if (cell->type == ID($and))
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new_a.replace(dict<SigBit,SigBit>{{State::Sx, State::S0}, {State::Sz, State::S0}}, &new_b);
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else if (cell->type == ID($or))
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new_a.replace(dict<SigBit,SigBit>{{State::Sx, State::S1}, {State::Sz, State::S1}}, &new_b);
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else log_abort();
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}
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log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a));
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module->connect(new_y, new_b);
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module->connect(new_conn);
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continue;
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}
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if (!keepdc && cell->type.in(ID($xor), ID($xnor)) && i == GRP_CONST_A) {
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if (cell->type.in(ID($xor), ID($xnor)) && i == GRP_CONST_A) {
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SigSpec undef_a, undef_y, undef_b;
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SigSpec def_y, def_a, def_b;
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for (int i = 0; i < GetSize(new_y); i++)
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if (new_a[i] == State::Sx || new_a[i] == State::Sz) {
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for (int i = 0; i < GetSize(new_y); i++) {
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bool undef = new_a[i] == State::Sx || new_a[i] == State::Sz;
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if (!keepdc && (undef || new_a[i] == new_b[i])) {
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undef_a.append(new_a[i]);
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if (cell->type == ID($xor))
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undef_b.append(State::S0);
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// For consistency with gate-level which does $xnor -> $_XOR_ + $_NOT_
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// For consistency since simplemap does $xnor -> $_XOR_ + $_NOT_
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else if (cell->type == ID($xnor))
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undef_b.append(State::S1);
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else log_abort();
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undef_y.append(new_y[i]);
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}
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else if (new_a[i] == State::S0 || new_a[i] == State::S1) {
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undef_a.append(new_a[i]);
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if (cell->type == ID($xor))
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undef_b.append(new_a[i] == State::S1 ? module->Not(NEW_ID, new_b[i]).as_bit() : new_b[i]);
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else if (cell->type == ID($xnor))
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undef_b.append(new_a[i] == State::S1 ? new_b[i] : module->Not(NEW_ID, new_b[i]).as_bit());
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else log_abort();
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undef_y.append(new_y[i]);
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}
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else {
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def_a.append(new_a[i]);
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def_b.append(new_b[i]);
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def_y.append(new_y[i]);
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}
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}
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if (!undef_y.empty()) {
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log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(undef_b), log_id(cell->type), log_signal(undef_a));
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module->connect(undef_y, undef_b);
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}
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if (def_y.empty()) {
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module->connect(new_conn);
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continue;
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if (def_y.empty()) {
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module->connect(new_conn);
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continue;
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}
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}
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new_a = std::move(def_a);
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new_b = std::move(def_b);
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@ -547,7 +574,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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}
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if (cell->type.in(ID($xnor), ID($_XNOR_))) {
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cover("opt.opt_expr.const_xnor");
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// For consistency with gate-level which does $xnor -> $_XOR_ + $_NOT_
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// For consistency since simplemap does $xnor -> $_XOR_ + $_NOT_
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replace_cell(assign_map, module, cell, "const_xnor", ID::Y, RTLIL::State::S1);
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goto next_cell;
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}
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@ -1151,9 +1178,6 @@ skip_fine_alu:
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if (b.is_fully_const() && b.as_bool() == false)
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identity_wrt_a = true;
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if (cell->type == ID($xor) && a == b)
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identity_wrt_a = true;
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}
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if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
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