riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Be mindful that sigmap(wire) could have dupes when checking \init

This commit is contained in:
Eddie Hung 2019-10-02 16:08:46 -07:00
parent c28d4b8047
commit f46ac1df9f
1 changed files with 4 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
passes/sat/sat.cc
View File

@ -265,15 +265,18 @@ struct SatHelper
RTLIL::SigSpec rhs = it.second->attributes.at("\\init");
log_assert(lhs.size() == rhs.size());
dict<RTLIL::SigBit,SigBit> seen_init;
RTLIL::SigSpec removed_bits;
for (int i = 0; i < lhs.size(); i++) {
RTLIL::SigSpec bit = lhs.extract(i, 1);
if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) {
if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit) || seen_init.at(bit, rhs[i]) != rhs[i]) {
removed_bits.append(bit);
lhs.remove(i, 1);
rhs.remove(i, 1);
i--;
}
else
seen_init[bit] = rhs[i];
}
if (removed_bits.size())