Merge pull request #1743 from YosysHQ/eddie/abc9_keep

abc9: improve (* keep *) handling

backends/aiger/xaiger.cc

@@ -174,11 +174,12 @@ struct XAigerWriter
 				undriven_bits.insert(bit);
 				unused_bits.insert(bit);
 
-				bool keep = wire->get_bool_attribute(ID::keep);
-				if (wire->port_input || keep)
+				bool scc = wire->attributes.count(ID(abc9_scc));
+				if (wire->port_input || scc)
 					input_bits.insert(bit);
 
-				if (wire->port_output || keep) {
+				bool keep = wire->get_bool_attribute(ID::keep);
+				if (wire->port_output || keep || scc) {
 					if (bit != wirebit)
 						alias_map[wirebit] = bit;
 					output_bits.insert(wirebit);
@@ -223,8 +224,6 @@ struct XAigerWriter
 					alias_map[Q] = D;
 					auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
 					log_assert(r.second);
-					if (input_bits.erase(Q))
-						log_assert(Q.wire->attributes.count(ID::keep));
 					continue;
 				}
 
@@ -378,11 +377,6 @@ struct XAigerWriter
 							alias_map[O] = b;
 						ci_bits.emplace_back(b);
 						undriven_bits.erase(O);
-						// If PI and CI, then must be a (* keep *) wire
-						if (input_bits.erase(O)) {
-							log_assert(output_bits.count(O));
-							log_assert(O.wire->get_bool_attribute(ID::keep));
-						}
 					}
 			}
 
@@ -467,8 +461,8 @@ struct XAigerWriter
 		for (const auto &bit : output_bits) {
 			ordered_outputs[bit] = aig_o++;
 			int aig;
-			// Unlike bit2aig() which checks aig_map first, for
-			//   inout/keep bits, since aig_map will point to
+			// Unlike bit2aig() which checks aig_map first for
+			//   inout/scc bits, since aig_map will point to
 			//   the PI, first attempt to find the NOT/AND driver
 			//   before resorting to an aig_map lookup (which
 			//   could be another PO)

passes/techmap/abc.cc

@@ -1553,6 +1553,11 @@ struct AbcPass : public Pass {
 		show_tempdir = design->scratchpad_get_bool("abc.showtmp", show_tempdir);
 		markgroups = design->scratchpad_get_bool("abc.markgroups", markgroups);
 
+		if (design->scratchpad_get_bool("abc.debug")) {
+			cleanup = false;
+			show_tempdir = true;
+		}
+
 		size_t argidx, g_argidx;
 		bool g_arg_from_cmd = false;
 		char pwd [PATH_MAX];

passes/techmap/abc9_ops.cc

@@ -93,9 +93,10 @@ void check(RTLIL::Design *design)
 void mark_scc(RTLIL::Module *module)
 {
 	// For every unique SCC found, (arbitrarily) find the first
-	//   cell in the component, and convert all wires driven by
-	//   its output ports into a new PO, and drive its previous
-	//   sinks with a new PI
+	//   cell in the component, and replace its output connections
+	//   with a new wire driven by the old connection but with a
+	//   special (* abc9_scc *) attribute set (which is used by
+	//   write_xaiger to break this wire into PI and POs)
 	pool<RTLIL::Const> ids_seen;
 	for (auto cell : module->cells()) {
 		auto it = cell->attributes.find(ID(abc9_scc_id));
@@ -109,15 +110,13 @@ void mark_scc(RTLIL::Module *module)
 		for (auto &c : cell->connections_) {
 			if (c.second.is_fully_const()) continue;
 			if (cell->output(c.first)) {
-				SigBit b = c.second.as_bit();
-				Wire *w = b.wire;
-				w->set_bool_attribute(ID::keep);
-				w->attributes[ID(abc9_scc_id)] = id.as_int();
+				Wire *w = module->addWire(NEW_ID, GetSize(c.second));
+				w->set_bool_attribute(ID(abc9_scc));
+				module->connect(w, c.second);
+				c.second = w;
 			}
 		}
 	}
-
-	module->fixup_ports();
 }
 
 void prep_dff(RTLIL::Module *module)
@@ -967,10 +966,8 @@ void reintegrate(RTLIL::Module *module)
 		RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
 		RTLIL::Wire *wire = module->wire(port);
 		log_assert(wire);
-		if (wire->attributes.erase(ID(abc9_scc_id))) {
-			auto r YS_ATTRIBUTE(unused) = wire->attributes.erase(ID::keep);
-			log_assert(r);
-		}
+		wire->attributes.erase(ID(abc9_scc));
+
 		RTLIL::Wire *remap_wire = module->wire(remap_name(port));
 		RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire));
 		log_assert(GetSize(signal) >= GetSize(remap_wire));