mirror of https://github.com/YosysHQ/yosys.git
opt_expr: extend to $xnor and $_XNOR_
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ee5995641e
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@ -496,17 +496,23 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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}
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}
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if (cell->type == ID($_XOR_) || (cell->type == ID($xor) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID(A_SIGNED)).as_bool()))
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if (cell->type.in(ID($_XOR_), ID($_XNOR_)) || (cell->type.in(ID($xor), ID($xnor)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID(A_SIGNED)).as_bool()))
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{
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SigBit sig_a = assign_map(cell->getPort(ID::A));
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SigBit sig_b = assign_map(cell->getPort(ID::B));
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if (!sig_a.wire)
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std::swap(sig_a, sig_b);
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if (sig_b == State::S0 || sig_b == State::S1) {
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cover("opt.opt_expr.xor_buffer");
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replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a);
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goto next_cell;
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}
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if (sig_b == State::S0 || sig_b == State::S1)
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if (cell->type.in(ID($xor), ID($_XOR_))) {
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cover("opt.opt_expr.xor_buffer");
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replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a);
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goto next_cell;
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}
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if (cell->type.in(ID($xnor), ID($_XNOR_))) {
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cover("opt.opt_expr.xnor_buffer");
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replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID, sig_a));
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goto next_cell;
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}
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}
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if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor), ID($neg)) &&
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@ -855,8 +861,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (input.match("11")) ACTION_DO_Y(0);
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if (input.match(" *")) ACTION_DO_Y(x);
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if (input.match("* ")) ACTION_DO_Y(x);
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if (input.match(" 0")) ACTION_DO(ID::Y, input.extract(1, 1));
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if (input.match("0 ")) ACTION_DO(ID::Y, input.extract(0, 1));
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}
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if (cell->type == ID($_MUX_)) {
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