mirror of https://github.com/YosysHQ/yosys.git
abc9_ops -prep_times: generate flop boxes from abc9_required attr
This commit is contained in:
Eddie Hung
parent
e0af812180
commit
475d983676
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@ -39,9 +39,13 @@ void check(RTLIL::Design *design)
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{
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dict<IdString,IdString> box_lookup;
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for (auto m : design->modules()) {
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auto flop = m->get_bool_attribute(ID(abc9_flop));
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auto it = m->attributes.find(ID(abc9_box_id));
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if (it == m->attributes.end())
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if (it == m->attributes.end()) {
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if (flop)
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log_error("Module '%s' contains (* abc9_flop *) but not (* abc9_box_id=<int> *).\n", log_id(m));
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continue;
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}
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if (m->name.begins_with("$paramod"))
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continue;
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auto id = it->second.as_int();
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@ -59,21 +63,31 @@ void check(RTLIL::Design *design)
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if (w->get_bool_attribute("\\abc9_carry")) {
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if (w->port_input) {
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if (carry_in != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
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log_error("Module '%s' contains more than one (* abc9_carry *) input port.\n", log_id(m));
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carry_in = port_name;
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}
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if (w->port_output) {
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if (carry_out != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(m));
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log_error("Module '%s' contains more than one (* abc9_carry *) output port.\n", log_id(m));
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carry_out = port_name;
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}
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}
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}
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if (carry_in != IdString() && carry_out == IdString())
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log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
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log_error("Module '%s' contains an (* abc9_carry *) input port but no output port.\n", log_id(m));
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if (carry_in == IdString() && carry_out != IdString())
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log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
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log_error("Module '%s' contains an (* abc9_carry *) output port but no input port.\n", log_id(m));
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if (flop) {
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int num_outputs = 0;
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for (auto port_name : m->ports) {
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auto wire = m->wire(port_name);
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if (wire->port_output) num_outputs++;
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}
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if (num_outputs != 1)
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log_error("Module '%s' with (* abc_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs);
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}
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}
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}
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@ -464,12 +478,10 @@ void prep_holes(RTLIL::Module *module, bool dff)
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void prep_times(RTLIL::Design *design)
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{
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std::set<int> delays;
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pool<Module*> flops;
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std::vector<Cell*> boxes;
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std::map<int,std::vector<int>> requireds;
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for (auto module : design->selected_modules()) {
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if (module->get_bool_attribute("\\abc9_holes"))
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continue;
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if (module->processes.size() > 0) {
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log("Skipping module %s as it contains processes.\n", log_id(module));
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continue;
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@ -485,10 +497,13 @@ void prep_times(RTLIL::Design *design)
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continue;
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if (!inst_module->get_blackbox_attribute())
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continue;
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// Only flop boxes are not combinatorial and may have required times,
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// however those times are captured by this flop box, no need to
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// add delay boxes
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if (cell->attributes.count(ID(abc9_box_id)))
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if (inst_module->get_bool_attribute(ID(abc9_flop))) {
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flops.insert(inst_module);
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continue;
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}
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// All remaining boxes are combinatorial and cannot
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// contain a required time
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if (inst_module->attributes.count(ID(abc9_box_id)))
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continue;
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boxes.emplace_back(cell);
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}
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@ -536,15 +551,48 @@ void prep_times(RTLIL::Design *design)
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std::stringstream ss;
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bool first = true;
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for (auto d : delays)
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if (first) {
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for (auto d : delays) {
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if (first)
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first = false;
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ss << d;
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}
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else
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ss << " " << d;
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ss << " ";
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ss << d;
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}
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module->attributes[ID(abc9_delays)] = ss.str();
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}
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std::stringstream ss;
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for (auto flop_module : flops) {
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// Skip parameterised flop_modules for now (since we do not
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// dynamically generate the abc9_box_id)
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if (flop_module->name.begins_with("$paramod"))
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continue;
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int num_inputs = 0, num_outputs = 0;
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for (auto port_name : flop_module->ports) {
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auto wire = flop_module->wire(port_name);
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if (wire->port_input) num_inputs++;
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if (wire->port_output) num_outputs++;
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}
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log_assert(num_outputs == 1);
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ss << log_id(flop_module) << " " << flop_module->attributes.at(ID(abc9_box_id)).as_int();
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ss << " 1 " << num_inputs+1 << " " << num_outputs << std::endl;
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bool first = true;
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for (auto port_name : flop_module->ports) {
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auto wire = flop_module->wire(port_name);
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if (!wire->port_input)
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continue;
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if (first)
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first = false;
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else
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ss << " ";
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ss << wire->attributes.at("\\abc9_required", 0).as_int();
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}
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// Last input is 'abc9_ff.Q'
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ss << " 0" << std::endl << std::endl;
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}
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design->scratchpad_set_string("abc9_ops.box.flops", ss.str());
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}
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void write_box(RTLIL::Module *module, const std::string &src, const std::string &dst) {
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@ -559,6 +607,8 @@ void write_box(RTLIL::Module *module, const std::string &src, const std::string
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ifs.close();
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}
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ofs << module->design->scratchpad_get_string("abc9_ops.box.flops");
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auto it = module->attributes.find(ID(abc9_delays));
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if (it != module->attributes.end()) {
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for (const auto &tok : split_tokens(it->second.decode_string())) {
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@ -62,67 +62,6 @@ $__ABC9_ASYNC1 1001 1 2 1
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#A S
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0 764 # Y
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# Flop boxes:
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# * Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
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# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
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# * Exception: $abc9_currQ is a special input (located last) necessary for clock-enable functionality
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# Box 1100 : FDRE
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# name ID w/b ins outs
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FDRE 1100 1 5 1
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#C CE D R $abc9_currQ
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#0 109 -46 404 0
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0 109 0 404 0 # Q (-46ps Tsu clamped to 0)
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# Box 1101 : FDRE_1
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# name ID w/b ins outs
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FDRE_1 1101 1 5 1
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#C CE D R $abc9_currQ
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#0 109 -46 404 0
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0 109 0 404 0 # Q (-46ps Tsu clamped to 0)
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# Box 1102 : FDSE
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# name ID w/b ins outs
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FDSE 1102 1 5 1
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#C CE D R $abc9_currQ
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#0 109 -46 404 0
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0 109 0 404 0 # Q (-46ps Tsu clamped to 0)
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# Box 1103 : FDSE_1
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# name ID w/b ins outs
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FDSE_1 1103 1 5 1
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#C CE D R $abc9_currQ
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#0 109 -46 404 0
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0 109 0 404 0 # Q (-46ps Tsu clamped to 0)
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# Box 1104 : FDCE
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# name ID w/b ins outs
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FDCE 1104 1 5 1
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#C CE CLR D $abc9_currQ
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#0 109 764 -46 0
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0 109 764 0 0 # Q (-46ps Tsu clamped to 0)
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# Box 1105 : FDCE_1
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# name ID w/b ins outs
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FDCE_1 1105 1 5 1
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#C CE CLR D $abc9_currQ
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#0 109 764 -46 0
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0 109 764 0 0 # Q (-46ps Tsu clamped to 0)
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# Box 1106 : FDPE
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# name ID w/b ins outs
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FDPE 1106 1 5 1
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#C CE D PRE $abc9_currQ
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#0 109 -46 764 0
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0 109 0 764 0 # Q (-46ps Tsu clamped to 0)
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# Box 1107 : FDPE_1
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# name ID w/b ins outs
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FDPE_1 1107 1 5 1
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#C CE D PRE $abc9_currQ
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#0 109 -46 764 0
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0 109 0 764 0 # Q (-46ps Tsu clamped to 0)
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# Box 2000 : $__ABC9_LUT6
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# (private cell to emulate async behaviour of LUTRAMs)
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# SLICEM/A6LUT
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