mirror of https://github.com/YosysHQ/yosys.git
xilinx/ecp5: disable abc9's "&mfs" optimisation
Can sometimes fire an assertion, e.g. #1962
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@ -219,6 +219,10 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
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for (size_t pos = abc9_script.find("{R}"); pos != std::string::npos; pos = abc9_script.find("{R}", pos))
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abc9_script = abc9_script.substr(0, pos) + R + abc9_script.substr(pos+3);
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if (design->scratchpad_get_bool("abc9.nomfs"))
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for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
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abc9_script = abc9_script.erase(pos, strlen("&mfs"));
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abc9_script += stringf("; &ps -l; &write -n %s/output.aig", tempdir_name.c_str());
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if (design->scratchpad_get_bool("abc9.verify")) {
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if (dff_mode)
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@ -324,6 +324,8 @@ struct SynthEcp5Pass : public ScriptPass
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if (abc9) {
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run("read_verilog -icells -lib -specify +/abc9_model.v +/ecp5/abc9_model.v");
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if (!help_mode && !active_design->scratchpad.count("abc9.nomfs"))
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active_design->scratchpad_set_bool("abc9.nomfs", true);
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if (nowidelut)
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run("abc9 -maxlut 4 -W 200");
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else
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@ -613,6 +613,8 @@ struct SynthXilinxPass : public ScriptPass
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if (family != "xc7")
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log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
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"will use timing for 'xc7' instead.\n", family.c_str());
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if (!help_mode && !active_design->scratchpad.count("abc9.nomfs"))
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active_design->scratchpad_set_bool("abc9.nomfs", true);
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std::string techmap_args = "-map +/xilinx/abc9_map.v -max_iter 1";
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if (dff_mode)
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techmap_args += " -D DFF_MODE";
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