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xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only

This commit is contained in:
Eddie Hung 2020-04-22 17:43:25 -07:00
parent db09e96dff
commit 592baebd22
1 changed files with 1 additions and 1 deletions
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2
passes/pmgen/xilinx_dsp_cascade.pmg
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@ -188,7 +188,7 @@ arg next
// driven by the 'P' output of the previous DSP cell, and (c) has its
// 'PCIN' port unused
match nextP
select !param(nextP, \CREG).as_bool()
select !nextP->type.in(\DSP48E1) || !param(nextP, \CREG).as_bool()
select (nextP->type.in(\DSP48A, \DSP48A1) && port(nextP, \OPMODE, Const(0, 8)).extract(2,2) == Const::from_string("11")) || (nextP->type.in(\DSP48E1) && port(nextP, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011"))
select nusers(port(nextP, \C, SigSpec())) > 1
select nusers(port(nextP, \PCIN, SigSpec())) == 0